Lines Matching refs:UINT64_CAST
125 #define MMC_FPROM_CYC_MASK (UINT64_CAST 31 << 49) /* of 'L' suffix, */
127 #define MMC_FPROM_WR_MASK (UINT64_CAST 31 << 44)
129 #define MMC_UCTLR_CYC_MASK (UINT64_CAST 31 << 39)
131 #define MMC_UCTLR_WR_MASK (UINT64_CAST 31 << 34)
133 #define MMC_DIMM0_SEL_MASK (UINT64_CAST 3 << 32)
135 #define MMC_IO_PROT_EN_MASK (UINT64_CAST 1 << 31)
136 #define MMC_IO_PROT (UINT64_CAST 1 << 31)
138 #define MMC_ARB_MLSS_MASK (UINT64_CAST 1 << 30)
139 #define MMC_ARB_MLSS (UINT64_CAST 1 << 30)
141 #define MMC_IGNORE_ECC_MASK (UINT64_CAST 1 << 29)
142 #define MMC_IGNORE_ECC (UINT64_CAST 1 << 29)
144 #define MMC_DIR_PREMIUM_MASK (UINT64_CAST 1 << 28)
145 #define MMC_DIR_PREMIUM (UINT64_CAST 1 << 28)
147 #define MMC_REPLY_GUAR_MASK (UINT64_CAST 15 << 24)
149 #define MMC_BANK_MASK(_b) (UINT64_CAST 7 << MMC_BANK_SHFT(_b))
151 #define MMC_RESET_DEFAULTS (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \
152 UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \
153 UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \
154 UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \
156 UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \
162 #define MRC_ENABLE_MASK (UINT64_CAST 1 << 63)
163 #define MRC_ENABLE (UINT64_CAST 1 << 63)
165 #define MRC_COUNTER_MASK (UINT64_CAST 0xfff << 12)
167 #define MRC_RESET_DEFAULTS (UINT64_CAST 0x400)
172 #define MDI_SELECT_MASK (UINT64_CAST 0x0f << 32)
173 #define MDI_DIMM_MODE_MASK (UINT64_CAST 0xfff)
178 #define MMS_RP_SIZE_MASK (UINT64_CAST 0x3f << 8)
180 #define MMS_RQ_SIZE_MASK (UINT64_CAST 0x1f)
186 #define MFC_VALID_MASK (UINT64_CAST 1 << 63)
187 #define MFC_VALID (UINT64_CAST 1 << 63)
189 #define MFC_ADDR_MASK (UINT64_CAST 0x3ffffff)
194 #define MLAN_PHI1_MASK (UINT64_CAST 0x7f << 27)
196 #define MLAN_PHI0_MASK (UINT64_CAST 0x7f << 27)
198 #define MLAN_PULSE_MASK (UINT64_CAST 0x3ff << 10)
200 #define MLAN_SAMPLE_MASK (UINT64_CAST 0xff << 2)
203 #define MLAN_DONE (UINT64_CAST 0x02)
204 #define MLAN_RD_DATA (UINT64_CAST 0x01)
205 #define MLAN_RESET_DEFAULTS (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \
206 UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
211 #define MSU_CORECLK_TST_MASK (UINT64_CAST 1 << 7)
212 #define MSU_CORECLK_TST (UINT64_CAST 1 << 7)
214 #define MSU_CORECLK_MASK (UINT64_CAST 1 << 6)
215 #define MSU_CORECLK (UINT64_CAST 1 << 6)
217 #define MSU_NETSYNC_MASK (UINT64_CAST 1 << 5)
218 #define MSU_NETSYNC (UINT64_CAST 1 << 5)
220 #define MSU_FPROMRDY_MASK (UINT64_CAST 1 << 4)
221 #define MSU_FPROMRDY (UINT64_CAST 1 << 4)
223 #define MSU_I2CINTR_MASK (UINT64_CAST 1 << 3)
224 #define MSU_I2CINTR (UINT64_CAST 1 << 3)
227 #define MSU_SN0_SLOTID_MASK (UINT64_CAST 7)
229 #define MSU_SN00_SLOTID_MASK (UINT64_CAST 0x80)
236 #define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
238 #define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
242 #define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
244 #define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
248 #define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
250 #define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
252 #define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
254 #define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18)
256 #define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
258 #define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
264 #define MD_BANK_MASK (UINT64_CAST 7 << 29)
265 #define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT) /* 512 MB */
266 #define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT)
278 #define MD_DIR_SHARED (UINT64_CAST 0x0) /* 000 */
279 #define MD_DIR_POISONED (UINT64_CAST 0x1) /* 001 */
280 #define MD_DIR_EXCLUSIVE (UINT64_CAST 0x2) /* 010 */
281 #define MD_DIR_BUSY_SHARED (UINT64_CAST 0x3) /* 011 */
282 #define MD_DIR_BUSY_EXCL (UINT64_CAST 0x4) /* 100 */
283 #define MD_DIR_WAIT (UINT64_CAST 0x5) /* 101 */
284 #define MD_DIR_UNOWNED (UINT64_CAST 0x7) /* 111 */
291 #define MD_DIR_FORCE_ECC (UINT64_CAST 1 << 63)
321 #define MD_PDIR_PTR_MASK (UINT64_CAST 0x7ff << 22)
325 #define MD_PDIR_VECMSB_MASK (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
329 #define MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff)
386 #define MD_PROT_RW (UINT64_CAST 0x6)
387 #define MD_PROT_RO (UINT64_CAST 0x3)
388 #define MD_PROT_NO (UINT64_CAST 0x0)
389 #define MD_PROT_BAD (UINT64_CAST 0x5)
402 #define MD_PPROT_IO_MASK (UINT64_CAST 7 << 45)
416 #define MD_PROT_MIGMD_IREL (UINT64_CAST 0x3 << 3)
417 #define MD_PROT_MIGMD_IABS (UINT64_CAST 0x2 << 3)
418 #define MD_PROT_MIGMD_PREL (UINT64_CAST 0x1 << 3)
419 #define MD_PROT_MIGMD_OFF (UINT64_CAST 0x0 << 3)
772 #define MMCE_ILL_MSG_MASK (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT)
774 #define MMCE_ILL_REV_MASK (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT)
776 #define MMCE_LONG_PACK_MASK (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT)
778 #define MMCE_SHORT_PACK_MASK (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT)
780 #define MMCE_BAD_DATA_MASK (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT)