Lines Matching +full:0 +full:x11c00000
57 #define NASID_BITMASK (0x1ffLL)
62 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
70 #define NASID_BITMASK (0xffLL)
76 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
106 #define BWIN_WIDGET_MASK 0x7
150 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
151 #define MISC_PROM_SIZE 0x200000
153 #define DIAG_BASE PHYS_TO_K0(0x01500000)
154 #define DIAG_SIZE 0x300000
156 #define ROUTE_BASE PHYS_TO_K0(0x01800000)
157 #define ROUTE_SIZE 0x200000
159 #define IP27PROM_FLASH_HDR PHYS_TO_K0(0x01300000)
160 #define IP27PROM_FLASH_DATA PHYS_TO_K0(0x01301000)
162 #define IP27PROM_CORP PHYS_TO_K0(0x01800000)
163 #define IP27PROM_CORP_SIZE 0x10000
164 #define IP27PROM_CORP_STK PHYS_TO_K0(0x01810000)
165 #define IP27PROM_CORP_STKSIZE 0x2000
166 #define IP27PROM_DECOMP_BUF PHYS_TO_K0(0x01900000)
167 #define IP27PROM_DECOMP_SIZE 0xfff00
169 #define IP27PROM_BASE PHYS_TO_K0(0x01a00000)
170 #define IP27PROM_BASE_MAPPED (UNCAC_BASE | 0x1fc00000)
171 #define IP27PROM_SIZE_MAX 0x100000
173 #define IP27PROM_PCFG PHYS_TO_K0(0x01b00000)
174 #define IP27PROM_PCFG_SIZE 0xd0000
175 #define IP27PROM_ERRDMP PHYS_TO_K1(0x01bd0000)
176 #define IP27PROM_ERRDMP_SIZE 0xf000
178 #define IP27PROM_INIT_START PHYS_TO_K1(0x01bd0000)
179 #define IP27PROM_CONSOLE PHYS_TO_K1(0x01bdf000)
180 #define IP27PROM_CONSOLE_SIZE 0x200
181 #define IP27PROM_NETUART PHYS_TO_K1(0x01bdf200)
182 #define IP27PROM_NETUART_SIZE 0x100
183 #define IP27PROM_UNUSED1 PHYS_TO_K1(0x01bdf300)
184 #define IP27PROM_UNUSED1_SIZE 0x500
185 #define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x01bdf800)
186 #define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x01bdfc00)
187 #define IP27PROM_STACK_A PHYS_TO_K0(0x01be0000)
188 #define IP27PROM_STACK_B PHYS_TO_K0(0x01bf0000)
191 #define IP27PROM_INIT_END PHYS_TO_K0(0x01c00000)
193 #define SLAVESTACK_BASE PHYS_TO_K0(0x01580000)
194 #define SLAVESTACK_SIZE 0x40000
196 #define ENETBUFS_BASE PHYS_TO_K0(0x01f80000)
197 #define ENETBUFS_SIZE 0x20000
199 #define IO6PROM_BASE PHYS_TO_K0(0x01c00000)
200 #define IO6PROM_SIZE 0x400000
201 #define IO6PROM_BASE_MAPPED (UNCAC_BASE | 0x11c00000)
202 #define IO6DPROM_BASE PHYS_TO_K0(0x01c00000)
203 #define IO6DPROM_SIZE 0x200000
205 #define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000)
206 #define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000)
226 #define FREEMEM_BASE PHYS_TO_K0(0x2000000)
235 #define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000)
236 #define IP27PROM_RESTART PHYS_TO_COMPATK1(0x1fc00008)
237 #define IP27PROM_SLAVELOOP PHYS_TO_COMPATK1(0x1fc00010)
238 #define IP27PROM_PODMODE PHYS_TO_COMPATK1(0x1fc00018)
239 #define IP27PROM_IOC3UARTPOD PHYS_TO_COMPATK1(0x1fc00020)
240 #define IP27PROM_FLASHLEDS PHYS_TO_COMPATK1(0x1fc00028)
241 #define IP27PROM_REPOD PHYS_TO_COMPATK1(0x1fc00030)
242 #define IP27PROM_LAUNCHSLAVE PHYS_TO_COMPATK1(0x1fc00038)
243 #define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040)
244 #define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048)
253 /* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
258 #define CACHE_ERR_EFRAME 0x480
260 #define CACHE_ERR_EFRAME 0x400
264 #define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */
265 #define CACHE_ERR_IBASE_PTR (0x1000 - 40)
279 #define OLD_ERR_STS_WAR_OFFSET ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100)