Lines Matching +full:0 +full:x0a40
46 * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
51 #define A_MC_BASE_0 0x0010051000
52 #define A_MC_BASE_1 0x0010052000
53 #define MC_REGISTER_SPACING 0x1000
58 #define R_MC_CONFIG 0x0000000100
59 #define R_MC_DRAMCMD 0x0000000120
60 #define R_MC_DRAMMODE 0x0000000140
61 #define R_MC_TIMING1 0x0000000160
62 #define R_MC_TIMING2 0x0000000180
63 #define R_MC_CS_START 0x00000001A0
64 #define R_MC_CS_END 0x00000001C0
65 #define R_MC_CS_INTERLEAVE 0x00000001E0
68 #define R_MC_CSX_BASE 0x0000000200
69 #define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */
70 #define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */
71 #define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */
72 #define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */
74 #define R_MC_CS0_ROW 0x0000000200
75 #define R_MC_CS0_COL 0x0000000220
76 #define R_MC_CS0_BA 0x0000000240
77 #define R_MC_CS1_ROW 0x0000000260
78 #define R_MC_CS1_COL 0x0000000280
79 #define R_MC_CS1_BA 0x00000002A0
80 #define R_MC_CS2_ROW 0x00000002C0
81 #define R_MC_CS2_COL 0x00000002E0
82 #define R_MC_CS2_BA 0x0000000300
83 #define R_MC_CS3_ROW 0x0000000320
84 #define R_MC_CS3_COL 0x0000000340
85 #define R_MC_CS3_BA 0x0000000360
86 #define R_MC_CS_ATTR 0x0000000380
87 #define R_MC_TEST_DATA 0x0000000400
88 #define R_MC_TEST_ECC 0x0000000420
89 #define R_MC_MCLK_CFG 0x0000000500
99 #define A_L2_READ_TAG 0x0010040018
100 #define A_L2_ECC_TAG 0x0010040038
102 #define A_L2_READ_MISC 0x0010040058
104 #define A_L2_WAY_DISABLE 0x0010041000
105 #define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
106 #define A_L2_MGMT_TAG_BASE 0x00D0000000
109 #define A_L2_CACHE_DISABLE 0x0010042000
110 #define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8))
111 #define A_L2_MISC_CONFIG 0x0010043000
127 #define A_PCI_TYPE00_HEADER 0x00DE000000
128 #define A_PCI_TYPE01_HEADER 0x00DE000800
136 #define A_MAC_BASE_0 0x0010064000
137 #define A_MAC_BASE_1 0x0010065000
139 #define A_MAC_BASE_2 0x0010066000
142 #define MAC_SPACING 0x1000
143 #define MAC_DMA_TXRX_SPACING 0x0400
144 #define MAC_DMA_CHANNEL_SPACING 0x0100
145 #define DMA_RX 0
161 #define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */
186 #define R_MAC_DMA_CONFIG0 0x00000000
187 #define R_MAC_DMA_CONFIG1 0x00000008
188 #define R_MAC_DMA_DSCR_BASE 0x00000010
189 #define R_MAC_DMA_DSCR_CNT 0x00000018
190 #define R_MAC_DMA_CUR_DSCRA 0x00000020
191 #define R_MAC_DMA_CUR_DSCRB 0x00000028
192 #define R_MAC_DMA_CUR_DSCRADDR 0x00000030
194 #define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */
201 #define R_MAC_RMON_TX_BYTES 0x00000000
202 #define R_MAC_RMON_COLLISIONS 0x00000008
203 #define R_MAC_RMON_LATE_COL 0x00000010
204 #define R_MAC_RMON_EX_COL 0x00000018
205 #define R_MAC_RMON_FCS_ERROR 0x00000020
206 #define R_MAC_RMON_TX_ABORT 0x00000028
207 /* Counter #6 (0x30) now reserved */
208 #define R_MAC_RMON_TX_BAD 0x00000038
209 #define R_MAC_RMON_TX_GOOD 0x00000040
210 #define R_MAC_RMON_TX_RUNT 0x00000048
211 #define R_MAC_RMON_TX_OVERSIZE 0x00000050
212 #define R_MAC_RMON_RX_BYTES 0x00000080
213 #define R_MAC_RMON_RX_MCAST 0x00000088
214 #define R_MAC_RMON_RX_BCAST 0x00000090
215 #define R_MAC_RMON_RX_BAD 0x00000098
216 #define R_MAC_RMON_RX_GOOD 0x000000A0
217 #define R_MAC_RMON_RX_RUNT 0x000000A8
218 #define R_MAC_RMON_RX_OVERSIZE 0x000000B0
219 #define R_MAC_RMON_RX_FCS_ERROR 0x000000B8
220 #define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0
221 #define R_MAC_RMON_RX_CODE_ERROR 0x000000C8
222 #define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0
225 #define R_MAC_CFG 0x00000100
226 #define R_MAC_THRSH_CFG 0x00000108
227 #define R_MAC_VLANTAG 0x00000110
228 #define R_MAC_FRAMECFG 0x00000118
229 #define R_MAC_EOPCNT 0x00000120
230 #define R_MAC_FIFO_PTRS 0x00000128
231 #define R_MAC_ADFILTER_CFG 0x00000200
232 #define R_MAC_ETHERNET_ADDR 0x00000208
233 #define R_MAC_PKT_TYPE 0x00000210
235 #define R_MAC_ADMASK0 0x00000218
236 #define R_MAC_ADMASK1 0x00000220
238 #define R_MAC_HASH_BASE 0x00000240
239 #define R_MAC_ADDR_BASE 0x00000280
240 #define R_MAC_CHLO0_BASE 0x00000300
241 #define R_MAC_CHUP0_BASE 0x00000320
242 #define R_MAC_ENABLE 0x00000400
243 #define R_MAC_STATUS 0x00000408
244 #define R_MAC_INT_MASK 0x00000410
245 #define R_MAC_TXD_CTL 0x00000420
246 #define R_MAC_MDIO 0x00000428
248 #define R_MAC_STATUS1 0x00000430
250 #define R_MAC_DEBUG_STATUS 0x00000448
265 #define A_DUART 0x0010060000
267 #define DUART_CHANREG_SPACING 0x100
273 #define R_DUART_MODE_REG_1 0x000
274 #define R_DUART_MODE_REG_2 0x010
275 #define R_DUART_STATUS 0x020
276 #define R_DUART_CLK_SEL 0x030
277 #define R_DUART_CMD 0x050
278 #define R_DUART_RX_HOLD 0x060
279 #define R_DUART_TX_HOLD 0x070
282 #define R_DUART_FULL_CTL 0x040
283 #define R_DUART_OPCR_X 0x080
284 #define R_DUART_AUXCTL_X 0x090
294 #define DUART_IMRISR_SPACING 0x20
295 #define DUART_INCHNG_SPACING 0x10
312 #define R_DUART_AUX_CTRL 0x010
313 #define R_DUART_ISR_A 0x020
314 #define R_DUART_IMR_A 0x030
315 #define R_DUART_ISR_B 0x040
316 #define R_DUART_IMR_B 0x050
317 #define R_DUART_OUT_PORT 0x060
318 #define R_DUART_OPCR 0x070
319 #define R_DUART_IN_PORT 0x080
321 #define R_DUART_SET_OPR 0x0B0
322 #define R_DUART_CLEAR_OPR 0x0C0
323 #define R_DUART_IN_CHNG_A 0x0D0
324 #define R_DUART_IN_CHNG_B 0x0E0
331 #define A_DUART_MODE_REG_1_A 0x0010060100
332 #define A_DUART_MODE_REG_2_A 0x0010060110
333 #define A_DUART_STATUS_A 0x0010060120
334 #define A_DUART_CLK_SEL_A 0x0010060130
335 #define A_DUART_CMD_A 0x0010060150
336 #define A_DUART_RX_HOLD_A 0x0010060160
337 #define A_DUART_TX_HOLD_A 0x0010060170
339 #define A_DUART_MODE_REG_1_B 0x0010060200
340 #define A_DUART_MODE_REG_2_B 0x0010060210
341 #define A_DUART_STATUS_B 0x0010060220
342 #define A_DUART_CLK_SEL_B 0x0010060230
343 #define A_DUART_CMD_B 0x0010060250
344 #define A_DUART_RX_HOLD_B 0x0010060260
345 #define A_DUART_TX_HOLD_B 0x0010060270
347 #define A_DUART_INPORT_CHNG 0x0010060300
348 #define A_DUART_AUX_CTRL 0x0010060310
349 #define A_DUART_ISR_A 0x0010060320
350 #define A_DUART_IMR_A 0x0010060330
351 #define A_DUART_ISR_B 0x0010060340
352 #define A_DUART_IMR_B 0x0010060350
353 #define A_DUART_OUT_PORT 0x0010060360
354 #define A_DUART_OPCR 0x0010060370
355 #define A_DUART_IN_PORT 0x0010060380
356 #define A_DUART_ISR 0x0010060390
357 #define A_DUART_IMR 0x00100603A0
358 #define A_DUART_SET_OPR 0x00100603B0
359 #define A_DUART_CLEAR_OPR 0x00100603C0
360 #define A_DUART_INPORT_CHNG_A 0x00100603D0
361 #define A_DUART_INPORT_CHNG_B 0x00100603E0
364 #define A_DUART_FULL_CTL_A 0x0010060140
365 #define A_DUART_FULL_CTL_B 0x0010060240
367 #define A_DUART_OPCR_A 0x0010060180
368 #define A_DUART_OPCR_B 0x0010060280
370 #define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0
381 #define A_SER_BASE_0 0x0010060400
382 #define A_SER_BASE_1 0x0010060800
383 #define SER_SPACING 0x400
385 #define SER_DMA_TXRX_SPACING 0x80
398 #define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */
414 #define R_SER_DMA_CONFIG0 0x00000000
415 #define R_SER_DMA_CONFIG1 0x00000008
416 #define R_SER_DMA_DSCR_BASE 0x00000010
417 #define R_SER_DMA_DSCR_CNT 0x00000018
418 #define R_SER_DMA_CUR_DSCRA 0x00000020
419 #define R_SER_DMA_CUR_DSCRB 0x00000028
420 #define R_SER_DMA_CUR_DSCRADDR 0x00000030
422 #define R_SER_DMA_CONFIG0_RX 0x00000000
423 #define R_SER_DMA_CONFIG1_RX 0x00000008
424 #define R_SER_DMA_DSCR_BASE_RX 0x00000010
425 #define R_SER_DMA_DSCR_COUNT_RX 0x00000018
426 #define R_SER_DMA_CUR_DSCR_A_RX 0x00000020
427 #define R_SER_DMA_CUR_DSCR_B_RX 0x00000028
428 #define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030
430 #define R_SER_DMA_CONFIG0_TX 0x00000080
431 #define R_SER_DMA_CONFIG1_TX 0x00000088
432 #define R_SER_DMA_DSCR_BASE_TX 0x00000090
433 #define R_SER_DMA_DSCR_COUNT_TX 0x00000098
434 #define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0
435 #define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8
436 #define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0
438 #define R_SER_MODE 0x00000100
439 #define R_SER_MINFRM_SZ 0x00000108
440 #define R_SER_MAXFRM_SZ 0x00000110
441 #define R_SER_ADDR 0x00000118
442 #define R_SER_USR0_ADDR 0x00000120
443 #define R_SER_USR1_ADDR 0x00000128
444 #define R_SER_USR2_ADDR 0x00000130
445 #define R_SER_USR3_ADDR 0x00000138
446 #define R_SER_CMD 0x00000140
447 #define R_SER_TX_RD_THRSH 0x00000160
448 #define R_SER_TX_WR_THRSH 0x00000168
449 #define R_SER_RX_RD_THRSH 0x00000170
450 #define R_SER_LINE_MODE 0x00000178
451 #define R_SER_DMA_ENABLE 0x00000180
452 #define R_SER_INT_MASK 0x00000190
453 #define R_SER_STATUS 0x00000188
454 #define R_SER_STATUS_DEBUG 0x000001A8
455 #define R_SER_RX_TABLE_BASE 0x00000200
457 #define R_SER_TX_TABLE_BASE 0x00000300
461 #define R_SER_RMON_TX_BYTE_LO 0x000001C0
462 #define R_SER_RMON_TX_BYTE_HI 0x000001C8
463 #define R_SER_RMON_RX_BYTE_LO 0x000001D0
464 #define R_SER_RMON_RX_BYTE_HI 0x000001D8
465 #define R_SER_RMON_TX_UNDERRUN 0x000001E0
466 #define R_SER_RMON_RX_OVERFLOW 0x000001E8
467 #define R_SER_RMON_RX_ERRORS 0x000001F0
468 #define R_SER_RMON_RX_BADADDR 0x000001F8
478 #define A_IO_EXT_BASE 0x0010061000
481 #define A_IO_EXT_CFG_BASE 0x0010061000
482 #define A_IO_EXT_MULT_SIZE_BASE 0x0010061100
483 #define A_IO_EXT_START_ADDR_BASE 0x0010061200
484 #define A_IO_EXT_TIME_CFG0_BASE 0x0010061600
485 #define A_IO_EXT_TIME_CFG1_BASE 0x0010061700
491 #define R_IO_EXT_CFG 0x0000
492 #define R_IO_EXT_MULT_SIZE 0x0100
493 #define R_IO_EXT_START_ADDR 0x0200
494 #define R_IO_EXT_TIME_CFG0 0x0600
495 #define R_IO_EXT_TIME_CFG1 0x0700
498 #define A_IO_INTERRUPT_STATUS 0x0010061A00
499 #define A_IO_INTERRUPT_DATA0 0x0010061A10
500 #define A_IO_INTERRUPT_DATA1 0x0010061A18
501 #define A_IO_INTERRUPT_DATA2 0x0010061A20
502 #define A_IO_INTERRUPT_DATA3 0x0010061A28
503 #define A_IO_INTERRUPT_ADDR0 0x0010061A30
504 #define A_IO_INTERRUPT_ADDR1 0x0010061A40
505 #define A_IO_INTERRUPT_PARITY 0x0010061A50
506 #define A_IO_PCMCIA_CFG 0x0010061A60
507 #define A_IO_PCMCIA_STATUS 0x0010061A70
508 #define A_IO_DRIVE_0 0x0010061300
509 #define A_IO_DRIVE_1 0x0010061308
510 #define A_IO_DRIVE_2 0x0010061310
511 #define A_IO_DRIVE_3 0x0010061318
517 #define R_IO_INTERRUPT_STATUS 0x0A00
518 #define R_IO_INTERRUPT_DATA0 0x0A10
519 #define R_IO_INTERRUPT_DATA1 0x0A18
520 #define R_IO_INTERRUPT_DATA2 0x0A20
521 #define R_IO_INTERRUPT_DATA3 0x0A28
522 #define R_IO_INTERRUPT_ADDR0 0x0A30
523 #define R_IO_INTERRUPT_ADDR1 0x0A40
524 #define R_IO_INTERRUPT_PARITY 0x0A50
525 #define R_IO_PCMCIA_CFG 0x0A60
526 #define R_IO_PCMCIA_STATUS 0x0A70
532 #define A_GPIO_CLR_EDGE 0x0010061A80
533 #define A_GPIO_INT_TYPE 0x0010061A88
534 #define A_GPIO_INPUT_INVERT 0x0010061A90
535 #define A_GPIO_GLITCH 0x0010061A98
536 #define A_GPIO_READ 0x0010061AA0
537 #define A_GPIO_DIRECTION 0x0010061AA8
538 #define A_GPIO_PIN_CLR 0x0010061AB0
539 #define A_GPIO_PIN_SET 0x0010061AB8
541 #define A_GPIO_BASE 0x0010061A80
543 #define R_GPIO_CLR_EDGE 0x00
544 #define R_GPIO_INT_TYPE 0x08
545 #define R_GPIO_INPUT_INVERT 0x10
546 #define R_GPIO_GLITCH 0x18
547 #define R_GPIO_READ 0x20
548 #define R_GPIO_DIRECTION 0x28
549 #define R_GPIO_PIN_CLR 0x30
550 #define R_GPIO_PIN_SET 0x38
556 #define A_SMB_XTRA_0 0x0010060000
557 #define A_SMB_XTRA_1 0x0010060008
558 #define A_SMB_FREQ_0 0x0010060010
559 #define A_SMB_FREQ_1 0x0010060018
560 #define A_SMB_STATUS_0 0x0010060020
561 #define A_SMB_STATUS_1 0x0010060028
562 #define A_SMB_CMD_0 0x0010060030
563 #define A_SMB_CMD_1 0x0010060038
564 #define A_SMB_START_0 0x0010060040
565 #define A_SMB_START_1 0x0010060048
566 #define A_SMB_DATA_0 0x0010060050
567 #define A_SMB_DATA_1 0x0010060058
568 #define A_SMB_CONTROL_0 0x0010060060
569 #define A_SMB_CONTROL_1 0x0010060068
570 #define A_SMB_PEC_0 0x0010060070
571 #define A_SMB_PEC_1 0x0010060078
573 #define A_SMB_0 0x0010060000
574 #define A_SMB_1 0x0010060008
575 #define SMB_REGISTER_SPACING 0x8
579 #define R_SMB_XTRA 0x0000000000
580 #define R_SMB_FREQ 0x0000000010
581 #define R_SMB_STATUS 0x0000000020
582 #define R_SMB_CMD 0x0000000030
583 #define R_SMB_START 0x0000000040
584 #define R_SMB_DATA 0x0000000050
585 #define R_SMB_CONTROL 0x0000000060
586 #define R_SMB_PEC 0x0000000070
596 #define A_SCD_WDOG_0 0x0010020050
597 #define A_SCD_WDOG_1 0x0010020150
598 #define SCD_WDOG_SPACING 0x100
603 #define R_SCD_WDOG_INIT 0x0000000000
604 #define R_SCD_WDOG_CNT 0x0000000008
605 #define R_SCD_WDOG_CFG 0x0000000010
607 #define A_SCD_WDOG_INIT_0 0x0010020050
608 #define A_SCD_WDOG_CNT_0 0x0010020058
609 #define A_SCD_WDOG_CFG_0 0x0010020060
611 #define A_SCD_WDOG_INIT_1 0x0010020150
612 #define A_SCD_WDOG_CNT_1 0x0010020158
613 #define A_SCD_WDOG_CFG_1 0x0010020160
619 #define A_SCD_TIMER_0 0x0010020070
620 #define A_SCD_TIMER_1 0x0010020078
621 #define A_SCD_TIMER_2 0x0010020170
622 #define A_SCD_TIMER_3 0x0010020178
624 #define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
627 #define R_SCD_TIMER_INIT 0x0000000000
628 #define R_SCD_TIMER_CNT 0x0000000010
629 #define R_SCD_TIMER_CFG 0x0000000020
631 #define A_SCD_TIMER_INIT_0 0x0010020070
632 #define A_SCD_TIMER_CNT_0 0x0010020080
633 #define A_SCD_TIMER_CFG_0 0x0010020090
635 #define A_SCD_TIMER_INIT_1 0x0010020078
636 #define A_SCD_TIMER_CNT_1 0x0010020088
637 #define A_SCD_TIMER_CFG_1 0x0010020098
639 #define A_SCD_TIMER_INIT_2 0x0010020170
640 #define A_SCD_TIMER_CNT_2 0x0010020180
641 #define A_SCD_TIMER_CFG_2 0x0010020190
643 #define A_SCD_TIMER_INIT_3 0x0010020178
644 #define A_SCD_TIMER_CNT_3 0x0010020188
645 #define A_SCD_TIMER_CFG_3 0x0010020198
648 #define A_SCD_SCRATCH 0x0010020C10
652 #define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000
653 #define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00
654 #define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08
661 #define A_SCD_SYSTEM_REVISION 0x0010020000
662 #define A_SCD_SYSTEM_CFG 0x0010020008
663 #define A_SCD_SYSTEM_MANUF 0x0010038000
669 #define A_ADDR_TRAP_INDEX 0x00100200B0
670 #define A_ADDR_TRAP_REG 0x00100200B8
671 #define A_ADDR_TRAP_UP_0 0x0010020400
672 #define A_ADDR_TRAP_UP_1 0x0010020408
673 #define A_ADDR_TRAP_UP_2 0x0010020410
674 #define A_ADDR_TRAP_UP_3 0x0010020418
675 #define A_ADDR_TRAP_DOWN_0 0x0010020420
676 #define A_ADDR_TRAP_DOWN_1 0x0010020428
677 #define A_ADDR_TRAP_DOWN_2 0x0010020430
678 #define A_ADDR_TRAP_DOWN_3 0x0010020438
679 #define A_ADDR_TRAP_CFG_0 0x0010020440
680 #define A_ADDR_TRAP_CFG_1 0x0010020448
681 #define A_ADDR_TRAP_CFG_2 0x0010020450
682 #define A_ADDR_TRAP_CFG_3 0x0010020458
684 #define A_ADDR_TRAP_REG_DEBUG 0x0010020460
698 #define A_IMR_CPU0_BASE 0x0010020000
699 #define A_IMR_CPU1_BASE 0x0010022000
700 #define IMR_REGISTER_SPACING 0x2000
706 #define R_IMR_INTERRUPT_DIAG 0x0010
707 #define R_IMR_INTERRUPT_LDT 0x0018
708 #define R_IMR_INTERRUPT_MASK 0x0028
709 #define R_IMR_INTERRUPT_TRACE 0x0038
710 #define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040
711 #define R_IMR_LDT_INTERRUPT_SET 0x0048
712 #define R_IMR_LDT_INTERRUPT 0x0018
713 #define R_IMR_LDT_INTERRUPT_CLR 0x0020
714 #define R_IMR_MAILBOX_CPU 0x00c0
715 #define R_IMR_ALIAS_MAILBOX_CPU 0x1000
716 #define R_IMR_MAILBOX_SET_CPU 0x00C8
717 #define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008
718 #define R_IMR_MAILBOX_CLR_CPU 0x00D0
719 #define R_IMR_INTERRUPT_STATUS_BASE 0x0100
721 #define R_IMR_INTERRUPT_MAP_BASE 0x0200
727 * for mbox_0_set_cpu2 returns 0x00100240C8
736 #define A_SCD_PERF_CNT_CFG 0x00100204C0
737 #define A_SCD_PERF_CNT_0 0x00100204D0
738 #define A_SCD_PERF_CNT_1 0x00100204D8
739 #define A_SCD_PERF_CNT_2 0x00100204E0
740 #define A_SCD_PERF_CNT_3 0x00100204E8
750 #define A_SCD_BUS_ERR_STATUS 0x0010020880
752 #define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0
753 #define A_BUS_ERR_STATUS_DEBUG 0x00100208D0
755 #define A_BUS_ERR_DATA_0 0x00100208A0
756 #define A_BUS_ERR_DATA_1 0x00100208A8
757 #define A_BUS_ERR_DATA_2 0x00100208B0
758 #define A_BUS_ERR_DATA_3 0x00100208B8
759 #define A_BUS_L2_ERRORS 0x00100208C0
760 #define A_BUS_MEM_IO_ERRORS 0x00100208C8
766 #define A_SCD_JTAG_BASE 0x0010000000
772 #define A_SCD_TRACE_CFG 0x0010020A00
773 #define A_SCD_TRACE_READ 0x0010020A08
774 #define A_SCD_TRACE_EVENT_0 0x0010020A20
775 #define A_SCD_TRACE_EVENT_1 0x0010020A28
776 #define A_SCD_TRACE_EVENT_2 0x0010020A30
777 #define A_SCD_TRACE_EVENT_3 0x0010020A38
778 #define A_SCD_TRACE_SEQUENCE_0 0x0010020A40
779 #define A_SCD_TRACE_SEQUENCE_1 0x0010020A48
780 #define A_SCD_TRACE_SEQUENCE_2 0x0010020A50
781 #define A_SCD_TRACE_SEQUENCE_3 0x0010020A58
782 #define A_SCD_TRACE_EVENT_4 0x0010020A60
783 #define A_SCD_TRACE_EVENT_5 0x0010020A68
784 #define A_SCD_TRACE_EVENT_6 0x0010020A70
785 #define A_SCD_TRACE_EVENT_7 0x0010020A78
786 #define A_SCD_TRACE_SEQUENCE_4 0x0010020A80
787 #define A_SCD_TRACE_SEQUENCE_5 0x0010020A88
788 #define A_SCD_TRACE_SEQUENCE_6 0x0010020A90
789 #define A_SCD_TRACE_SEQUENCE_7 0x0010020A98
804 #define A_DM_0 0x0010020B00
805 #define A_DM_1 0x0010020B20
806 #define A_DM_2 0x0010020B40
807 #define A_DM_3 0x0010020B60
808 #define DM_REGISTER_SPACING 0x20
813 #define R_DM_DSCR_BASE 0x0000000000
814 #define R_DM_DSCR_COUNT 0x0000000008
815 #define R_DM_CUR_DSCR_ADDR 0x0000000010
816 #define R_DM_DSCR_BASE_DEBUG 0x0000000018
819 #define A_DM_PARTIAL_0 0x0010020ba0
820 #define A_DM_PARTIAL_1 0x0010020ba8
821 #define A_DM_PARTIAL_2 0x0010020bb0
822 #define A_DM_PARTIAL_3 0x0010020bb8
823 #define DM_PARTIAL_REGISTER_SPACING 0x8
828 #define A_DM_CRC_0 0x0010020b80
829 #define A_DM_CRC_1 0x0010020b90
830 #define DM_CRC_REGISTER_SPACING 0x10
835 #define R_CRC_DEF_0 0x00
836 #define R_CTCP_DEF_0 0x08
844 #define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000)
846 #define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000)
847 #define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000)
848 #define A_PHYS_GENBUS _SB_MAKE64(0x0010090000)
849 #define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000)
850 #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)
851 #define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000)
852 #define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000)
853 #define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000)
854 #define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000)
855 #define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000)
856 #define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000)
857 #define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000)
858 #define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000)
859 #define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000)
860 #define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000)
861 #define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000)
862 #define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000)
864 #define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000)
865 #define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000)
866 #define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000)
867 #define A_PHYS_RESERVED _SB_MAKE64(0xF200000000)
868 #define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000)
870 #define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000)
872 #define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000)
873 #define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000)
874 #define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000)
875 #define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000)
876 #define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000)