Lines Matching +full:dma +full:- +full:mem
22 #define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */
32 #define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
33 #define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */
34 #define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
35 #define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
36 #define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
64 #define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */
65 #define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */
75 #define SGIMC_GIOPAR_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */
76 #define SGIMC_GIOPAR_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */
77 #define SGIMC_GIOPAR_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */
78 #define SGIMC_GIOPAR_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */
79 #define SGIMC_GIOPAR_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */
80 #define SGIMC_GIOPAR_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */
110 volatile u32 cmacc; /* Mem access config for CPU */
112 volatile u32 gmacc; /* Mem access config for GIO */
146 volatile u32 syssembit; /* Uni-bit system semaphore */
152 /* GIO dma control registers. */
154 volatile u32 gio_dma_trans; /* DMA mask to translation GIO addrs */
156 volatile u32 gio_dma_sbits; /* DMA GIO addr substitution bits */
158 volatile u32 dma_intr_cause; /* DMA IRQ cause indicator bits */
160 volatile u32 dma_ctrl; /* Main DMA control reg */
162 /* DMA TLB entry 0 */
168 /* DMA TLB entry 1 */
174 /* DMA TLB entry 2 */
180 /* DMA TLB entry 3 */
191 u32 _unused36[0x1000/4-2*4];
194 volatile u32 maddronly; /* Address DMA goes at */
198 volatile u32 dmasz; /* DMA count */
200 volatile u32 ssize; /* DMA stride size */
202 volatile u32 gmaddronly; /* Set GIO DMA but don't start trans */
204 volatile u32 dmaddnpgo; /* Set GIO DMA addr + start transfer */
206 volatile u32 dmamode; /* DMA mode config bit settings */
208 volatile u32 dmaccount; /* Zoom and byte count for DMA */
212 volatile u32 dmarunning; /* DMA op is in progress */
214 volatile u32 maddrdefstart; /* Set dma addr, defaults, and kick it */