Lines Matching +full:use +full:- +full:dma +full:- +full:tx
18 /* An HPC DMA descriptor. */
22 #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
24 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
27 #define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
29 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
31 #define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
36 /* The set of regs for each HPC3 PBUS DMA channel. */
38 volatile u32 pbdma_bptr; /* pbus dma channel buffer ptr */
39 volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
40 u32 _unused0[0x1000/4 - 2]; /* padding */
41 volatile u32 pbdma_ctrl; /* pbus dma channel control register has
50 #define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */
51 #define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */
53 #define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
63 volatile u32 cbptr; /* current dma buffer ptr, diagnostic use only */
64 volatile u32 ndptr; /* next dma descriptor ptr */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
72 #define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */
73 #define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
74 #define HPC3_SCTRL_DIR 0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
76 #define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
77 #define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */
78 #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
83 volatile u32 dconfig; /* DMA configuration register */
84 #define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
88 #define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
89 #define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
90 #define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
91 #define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
100 #define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
103 #define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
105 u32 _unused1[0x1000/4 - 6]; /* padding */
111 volatile u32 rx_cbptr; /* current dma buffer ptr, diagnostic use only */
112 volatile u32 rx_ndptr; /* next dma descriptor ptr */
113 u32 _unused0[0x1000/4 - 2]; /* padding */
123 #define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
124 #define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
132 #define HPC3_ERST_CRESET 0x1 /* Reset dma channel and external controller */
136 volatile u32 dconfig; /* DMA configuration register */
152 u32 _unused2[0x1000/4 - 8]; /* padding */
155 volatile u32 tx_cbptr; /* current dma buffer ptr, diagnostic use only */
156 volatile u32 tx_ndptr; /* next dma descriptor ptr */
157 u32 _unused3[0x1000/4 - 2]; /* padding */
166 #define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */
169 #define HPC3_ETXCTRL_ENDIAN 0x00000100 /* DMA channel endian mode, 1=little 0=big */
170 #define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */
175 u32 _unused4[0x1000/4 - 4]; /* padding */
179 /* First regs for the PBUS 8 dma channels. */
185 /* The SEEQ hpc3 ethernet dma/control registers. */
198 * you it was a peculiar bug. ;-)
201 #define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */
207 #define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
219 #define HPC3_BESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */
221 #define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */
223 u32 _unused1[0x14000/4 - 5]; /* padding */
225 /* Now direct PIO per-HPC3 peripheral access to external regs. */
233 /* Per-peripheral device external registers and DMA/PIO control. */
254 /* Enable 16-bit DMA access mode */
260 /* 5 bit burst count for DMA device */
263 /* Use live pbus_dreq unsynchronized signal */
284 /* Enable 16-bit PIO accesses */
293 u32 _unused5[0x0800/4 - 1];
297 u32 _unused6[0x0800/4 - 1];
301 u32 _unused7[0x1000/4 - 1];
304 volatile u32 bbram[8192-50-14]; /* Battery backed ram */