Lines Matching +full:external +full:- +full:bus
40 u32 _unused0[0x1000/4 - 2]; /* padding */
53 #define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
61 /* The HPC3 SCSI registers, this does not include external ones. */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
78 #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
89 #define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
100 #define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
105 u32 _unused1[0x1000/4 - 6]; /* padding */
113 u32 _unused0[0x1000/4 - 2]; /* padding */
132 #define HPC3_ERST_CRESET 0x1 /* Reset dma channel and external controller */
152 u32 _unused2[0x1000/4 - 8]; /* padding */
157 u32 _unused3[0x1000/4 - 2]; /* padding */
175 u32 _unused4[0x1000/4 - 4]; /* padding */
198 * you it was a peculiar bug. ;-)
201 #define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */
206 #define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
217 volatile u32 bestat; /* Bus error interrupt status reg. */
218 #define HPC3_BESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */
219 #define HPC3_BESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */
223 u32 _unused1[0x14000/4 - 5]; /* padding */
225 /* Now direct PIO per-HPC3 peripheral access to external regs. */
226 volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */
228 volatile u32 scsi1_ext[256]; /* SCSI channel 1 external regs */
230 volatile u32 eth_ext[320]; /* Ethernet external registers */
233 /* Per-peripheral device external registers and DMA/PIO control. */
254 /* Enable 16-bit DMA access mode */
256 /* Places halfwords on high 16 bits of bus */
284 /* Enable 16-bit PIO accesses */
293 u32 _unused5[0x0800/4 - 1];
297 u32 _unused6[0x0800/4 - 1];
301 u32 _unused7[0x1000/4 - 1];
304 volatile u32 bbram[8192-50-14]; /* Battery backed ram */