Lines Matching +full:0 +full:x0402
39 #define TASK_SIZE 0x80000000UL
55 #define TASK_SIZE32 0x7fff8000UL
57 #define TASK_SIZE64 (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
59 #define TASK_SIZE64 0x10000000000UL
139 {0,} \
158 /* DMFC2 rt, 0x0201 */
160 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
162 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
164 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
166 /* DMFC2 rt, 0x0084 */
168 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
170 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
172 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
174 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
176 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
177 * rt, 0x0107 */
179 /* DMFC2 rt, 0x0110 */
181 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
183 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
184 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
185 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
186 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
187 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
189 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
190 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
191 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
193 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
195 /* DMFC2 rt, 0x025E - Pass2 */
197 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
199 /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
203 .cp2 = {0,},
206 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
269 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
278 .emulated_fp = 0, \
287 .fpr = {{{0,},},}, \
288 .fcr31 = 0, \
289 .msacsr = 0, \
293 .bd_emu_branch_pc = 0, \
294 .bd_emu_cont_pc = 0,
303 .reg16 = 0, \
304 .reg17 = 0, \
305 .reg18 = 0, \
306 .reg19 = 0, \
307 .reg20 = 0, \
308 .reg21 = 0, \
309 .reg22 = 0, \
310 .reg23 = 0, \
311 .reg29 = 0, \
312 .reg30 = 0, \
313 .reg31 = 0, \
317 .cp0_status = 0, \
330 .dspr = {0, }, \
331 .dspcontrol = 0, \
336 .watch = {{{0,},},}, \
340 .cp0_badvaddr = 0, \
341 .cp0_baduaddr = 0, \
342 .error_code = 0, \
343 .trap_nr = 0, \
382 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
387 #define prefetch(x) __builtin_prefetch((x), 0, 1)