6  * bridge.h - bridge chip header file, derived from IRIX <sys/PCI/bridge.h>,
26 #define IOPGOFF(x)		((x) & (IOPGSIZE-1))
72 	/* Local Registers			       0x000000-0x00FFFF */
74 	/* standard widget configuration	       0x000000-0x000057 */
91 	/* bridge-specific widget configuration 0x000058-0x00007F */
102 	/* PMU & Map 0x000080-0x00008F */
107 	/* SSRAM 0x000090-0x00009F */
112 	/* Arbitration 0x0000A0-0x0000AF */
117 	/* Number In A Can 0x0000B0-0x0000BF */
122 	/* PCI/GIO 0x0000C0-0x0000FF */
137 	/* Interrupt 0x000100-0x0001FF */
158 	/* Device 0x000200-0x0003FF */
161 		u32	reg;			/* 0x0002{04,,,3C} */  member
166 		u32	reg;			/* 0x0002{44,,,7C} */  member
171 		u32	reg;			/* 0x0002{84,,,8C} */  member
173 #define b_even_resp	b_rrb_map[0].reg		/* 0x000284 */
174 #define b_odd_resp	b_rrb_map[1].reg		/* 0x00028C */
183 	char		_pad_000300[0x10000 - 0x000300];
185 	/* Internal Address Translation Entry RAM 0x010000-0x0103FF */
187 		u64	wr;			/* write-only */
190 			u32	rd;		/* read-only */
194 	char	_pad_010400[0x11000 - 0x010400];
196 	/* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
199 		u32	rd;		/* read-only */
202 	char	_pad_011400[0x20000 - 0x011400];
204 	/* PCI Device Configuration Spaces 0x020000-0x027FFF */
218 	/* PCI Type 1 Configuration Space 0x028000-0x028FFF */
224 	} b_type1_cfg;					/* 0x028000-0x029000 */
226 	char	_pad_029000[0x007000];			/* 0x029000-0x030000 */
236 	u8	_pad_030007[0x04fff8];			/* 0x030008-0x07FFFF */
238 	/* External Address Translation Entry RAM 0x080000-0x0FFFFF */
241 	/* Reserved 0x100000-0x1FFFFF */
242 	char	_pad_100000[0x200000-0x100000];
244 	/* PCI/GIO Device Spaces 0x200000-0xBFFFFF */
258 	/* External Flash Proms 1,0 0xC00000-0xFFFFFF */
260 		u8	c[0x400000 / 1];	/* read-only */
261 		u16	s[0x400000 / 2];	/* read-write */
262 		u32	l[0x400000 / 4];	/* read-only */
263 		u64	d[0x400000 / 8];	/* read-only */
295  * regularly against the offsets of the like-named fields
318 #define BRIDGE_DIR_MAP		0x000084	/* Direct Map reg */
322 #define BRIDGE_ARB		0x0000A4	/* Arbitration Priority reg */
328 #define BRIDGE_PCI_CFG		0x0000CC	/* PCI Type 1 Config reg */
339 #define BRIDGE_INT_ADDR0	0x000134	/* Host Address Reg */
354 #define BRIDGE_RESP_STATUS	0x000294	/* Read Response Status reg */
355 #define BRIDGE_RESP_CLEAR	0x00029C	/* Read Response Clear reg */
375 /* Byte offset macros for Bridge device IO spaces */
386 #define BRIDGE_DEVIO(x)		((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDG…
482 /* Bridge Bus time-out register bits definition */
791 		((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
793 /* 64-bit address attribute masks */
816 	((struct bridge_controller *)((bus)->sysdata))
818 #define bridge_read(bc, reg)		__raw_readl(&bc->base->reg)  argument
819 #define bridge_write(bc, reg, val)	__raw_writel(val, &bc->base->reg)  argument
820 #define bridge_set(bc, reg, val)	\  argument
821 	__raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg)
822 #define bridge_clr(bc, reg, val)	\  argument
823 	__raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)