Lines Matching +full:0 +full:xe00000
30 #define BRIDGE_ATE_RAM_SIZE 0x00000400 /* 1kB ATE RAM */
32 #define BRIDGE_CONFIG_BASE 0x20000
33 #define BRIDGE_CONFIG1_BASE 0x28000
34 #define BRIDGE_CONFIG_END 0x30000
35 #define BRIDGE_CONFIG_SLOT_SIZE 0x1000
37 #define BRIDGE_SSRAM_512K 0x00080000 /* 512kB */
38 #define BRIDGE_SSRAM_128K 0x00020000 /* 128kB */
39 #define BRIDGE_SSRAM_64K 0x00010000 /* 64kB */
40 #define BRIDGE_SSRAM_0K 0x00000000 /* 0kB */
48 #define ATE_V 0x01
49 #define ATE_CO 0x02
50 #define ATE_PREC 0x04
51 #define ATE_PREF 0x08
52 #define ATE_BAR 0x10
58 #define mkate(xaddr, xid, attr) (((xaddr) & 0x0000fffffffff000ULL) | \
72 /* Local Registers 0x000000-0x00FFFF */
74 /* standard widget configuration 0x000000-0x000057 */
75 widget_cfg_t b_widget; /* 0x000000 */
91 /* bridge-specific widget configuration 0x000058-0x00007F */
93 u32 b_wid_aux_err; /* 0x00005C */
95 u32 b_wid_resp_upper; /* 0x000064 */
97 u32 b_wid_resp_lower; /* 0x00006C */
99 u32 b_wid_tst_pin_ctrl; /* 0x000074 */
102 /* PMU & Map 0x000080-0x00008F */
104 u32 b_dir_map; /* 0x000084 */
107 /* SSRAM 0x000090-0x00009F */
109 u32 b_ram_perr; /* 0x000094 */
112 /* Arbitration 0x0000A0-0x0000AF */
114 u32 b_arb; /* 0x0000A4 */
117 /* Number In A Can 0x0000B0-0x0000BF */
119 u32 b_nic; /* 0x0000B4 */
122 /* PCI/GIO 0x0000C0-0x0000FF */
124 u32 b_bus_timeout; /* 0x0000C4 */
128 u32 b_pci_cfg; /* 0x0000CC */
130 u32 b_pci_err_upper; /* 0x0000D4 */
132 u32 b_pci_err_lower; /* 0x0000DC */
137 /* Interrupt 0x000100-0x0001FF */
139 u32 b_int_status; /* 0x000104 */
141 u32 b_int_enable; /* 0x00010C */
143 u32 b_int_rst_stat; /* 0x000114 */
145 u32 b_int_mode; /* 0x00011C */
147 u32 b_int_device; /* 0x000124 */
149 u32 b_int_host_err; /* 0x00012C */
152 u32 __pad; /* 0x0001{30,,,68} */
153 u32 addr; /* 0x0001{34,,,6C} */
154 } b_int_addr[8]; /* 0x000130 */
158 /* Device 0x000200-0x0003FF */
160 u32 __pad; /* 0x0002{00,,,38} */
161 u32 reg; /* 0x0002{04,,,3C} */
162 } b_device[8]; /* 0x000200 */
165 u32 __pad; /* 0x0002{40,,,78} */
166 u32 reg; /* 0x0002{44,,,7C} */
167 } b_wr_req_buf[8]; /* 0x000240 */
170 u32 __pad; /* 0x0002{80,,,88} */
171 u32 reg; /* 0x0002{84,,,8C} */
172 } b_rrb_map[2]; /* 0x000280 */
173 #define b_even_resp b_rrb_map[0].reg /* 0x000284 */
174 #define b_odd_resp b_rrb_map[1].reg /* 0x00028C */
177 u32 b_resp_status; /* 0x000294 */
179 u32 b_resp_clear; /* 0x00029C */
183 char _pad_000300[0x10000 - 0x000300];
185 /* Internal Address Translation Entry RAM 0x010000-0x0103FF */
194 char _pad_010400[0x11000 - 0x010400];
196 /* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
202 char _pad_011400[0x20000 - 0x011400];
204 /* PCI Device Configuration Spaces 0x020000-0x027FFF */
206 u8 c[0x1000 / 1];
207 u16 s[0x1000 / 2];
208 u32 l[0x1000 / 4];
209 u64 d[0x1000 / 8];
211 u8 c[0x100 / 1];
212 u16 s[0x100 / 2];
213 u32 l[0x100 / 4];
214 u64 d[0x100 / 8];
216 } b_type0_cfg_dev[8]; /* 0x020000 */
218 /* PCI Type 1 Configuration Space 0x028000-0x028FFF */
220 u8 c[0x1000 / 1];
221 u16 s[0x1000 / 2];
222 u32 l[0x1000 / 4];
223 u64 d[0x1000 / 8];
224 } b_type1_cfg; /* 0x028000-0x029000 */
226 char _pad_029000[0x007000]; /* 0x029000-0x030000 */
228 /* PCI Interrupt Acknowledge Cycle 0x030000 */
234 } b_pci_iack; /* 0x030000 */
236 u8 _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */
238 /* External Address Translation Entry RAM 0x080000-0x0FFFFF */
239 u64 b_ext_ate_ram[0x10000];
241 /* Reserved 0x100000-0x1FFFFF */
242 char _pad_100000[0x200000-0x100000];
244 /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */
246 u8 c[0x100000 / 1];
247 u16 s[0x100000 / 2];
248 u32 l[0x100000 / 4];
249 u64 d[0x100000 / 8];
250 } b_devio_raw[10]; /* 0x200000 */
258 /* External Flash Proms 1,0 0xC00000-0xFFFFFF */
260 u8 c[0x400000 / 1]; /* read-only */
261 u16 s[0x400000 / 2]; /* read-write */
262 u32 l[0x400000 / 4]; /* read-only */
263 u64 d[0x400000 / 8]; /* read-only */
264 } b_external_flash; /* 0xC00000 */
313 #define BRIDGE_WID_AUX_ERR 0x00005C /* Aux Error Command Word */
314 #define BRIDGE_WID_RESP_UPPER 0x000064 /* Response Buf Upper Addr */
315 #define BRIDGE_WID_RESP_LOWER 0x00006C /* Response Buf Lower Addr */
316 #define BRIDGE_WID_TST_PIN_CTRL 0x000074 /* Test pin control */
318 #define BRIDGE_DIR_MAP 0x000084 /* Direct Map reg */
320 #define BRIDGE_RAM_PERR 0x000094 /* SSRAM Parity Error */
322 #define BRIDGE_ARB 0x0000A4 /* Arbitration Priority reg */
324 #define BRIDGE_NIC 0x0000B4 /* Number In A Can */
326 #define BRIDGE_BUS_TIMEOUT 0x0000C4 /* Bus Timeout Register */
328 #define BRIDGE_PCI_CFG 0x0000CC /* PCI Type 1 Config reg */
329 #define BRIDGE_PCI_ERR_UPPER 0x0000D4 /* PCI error Upper Addr */
330 #define BRIDGE_PCI_ERR_LOWER 0x0000DC /* PCI error Lower Addr */
332 #define BRIDGE_INT_STATUS 0x000104 /* Interrupt Status */
333 #define BRIDGE_INT_ENABLE 0x00010C /* Interrupt Enables */
334 #define BRIDGE_INT_RST_STAT 0x000114 /* Reset Intr Status */
335 #define BRIDGE_INT_MODE 0x00011C /* Interrupt Mode */
336 #define BRIDGE_INT_DEVICE 0x000124 /* Interrupt Device */
337 #define BRIDGE_INT_HOST_ERR 0x00012C /* Host Error Field */
339 #define BRIDGE_INT_ADDR0 0x000134 /* Host Address Reg */
340 #define BRIDGE_INT_ADDR_OFF 0x000008 /* Host Addr offset (1..7) */
343 #define BRIDGE_DEVICE0 0x000204 /* Device 0 */
344 #define BRIDGE_DEVICE_OFF 0x000008 /* Device offset (1..7) */
347 #define BRIDGE_WR_REQ_BUF0 0x000244 /* Write Request Buffer 0 */
348 #define BRIDGE_WR_REQ_BUF_OFF 0x000008 /* Buffer Offset (1..7) */
351 #define BRIDGE_EVEN_RESP 0x000284 /* Even Device Response Buf */
352 #define BRIDGE_ODD_RESP 0x00028C /* Odd Device Response Buf */
354 #define BRIDGE_RESP_STATUS 0x000294 /* Read Response Status reg */
355 #define BRIDGE_RESP_CLEAR 0x00029C /* Read Response Clear reg */
359 #define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */
361 #define BRIDGE_TYPE0_CFG_DEV0 0x00020000 /* Type 0 Cfg, Device 0 */
362 #define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000 /* Type 0 Cfg Slot Offset (1..7) */
363 #define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */
370 #define BRIDGE_TYPE1_CFG 0x00028000 /* Type 1 Cfg space */
372 #define BRIDGE_PCI_IACK 0x00030000 /* PCI Interrupt Ack */
373 #define BRIDGE_EXT_SSRAM 0x00080000 /* Extern SSRAM (ATE) */
378 #define BRIDGE_DEVIO0 0x00200000 /* Device IO 0 Addr */
379 #define BRIDGE_DEVIO1 0x00400000 /* Device IO 1 Addr */
380 #define BRIDGE_DEVIO2 0x00600000 /* Device IO 2 Addr */
381 #define BRIDGE_DEVIO_OFF 0x00100000 /* Device IO Offset (3..7) */
383 #define BRIDGE_DEVIO_2MB 0x00200000 /* Device IO Offset (0..1) */
384 #define BRIDGE_DEVIO_1MB 0x00100000 /* Device IO Offset (2..7) */
388 #define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */
395 #define BRIDGE_WIDGET_PART_NUM 0xc002
396 #define XBRIDGE_WIDGET_PART_NUM 0xd002
399 #define BRIDGE_WIDGET_MFGR_NUM 0x036
400 #define XBRIDGE_WIDGET_MFGR_NUM 0x024
403 #define BRIDGE_REV_A 0x1
404 #define BRIDGE_REV_B 0x2
405 #define BRIDGE_REV_C 0x3
406 #define BRIDGE_REV_D 0x4
410 #define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24)
411 #define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16)
412 #define BRIDGE_STAT_FLASH_SELECT (0x1 << 6)
413 #define BRIDGE_STAT_PCI_GIO_N (0x1 << 5)
414 #define BRIDGE_STAT_PENDING (0x1F << 0)
417 #define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31)
418 #define BRIDGE_CTRL_EN_CLK50 (0x1 << 30)
419 #define BRIDGE_CTRL_EN_CLK40 (0x1 << 29)
420 #define BRIDGE_CTRL_EN_CLK33 (0x1 << 28)
422 #define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF))
423 #define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x)))
424 #define BRIDGE_CTRL_IO_SWAP (0x1 << 23)
425 #define BRIDGE_CTRL_MEM_SWAP (0x1 << 22)
426 #define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21)
427 #define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20)
428 #define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19)
430 #define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3))
431 #define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3))
432 #define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2))
433 #define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1))
434 #define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0))
435 #define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16)
437 #define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
438 #define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11)
439 #define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10)
440 #define BRIDGE_CTRL_SYS_END (0x1 << 9)
442 #define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f))
443 #define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0)
444 #define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf))
448 #define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
450 #define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
451 #define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF)
463 #define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
464 #define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)
465 #define BRIDGE_DIRMAP_ADD512 (0x1 << 17)
466 #define BRIDGE_DIRMAP_OFF (0x1ffff << 0)
471 #define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3)
473 #define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff)
480 #define BRIDGE_ARB_LPRI_RING_B0 (1 << 0)
484 #define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
486 #define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0)
487 #define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
490 #define BRIDGE_ISR_MULTI_ERR (0x1u << 31)
491 #define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30)
492 #define BRIDGE_ISR_UNEXP_RESP (0x1 << 29)
493 #define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28)
494 #define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27)
495 #define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26)
496 #define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25)
497 #define BRIDGE_ISR_INVLD_ADDR (0x1 << 24)
498 #define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23)
499 #define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22)
500 #define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21)
501 #define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20)
502 #define BRIDGE_ISR_LLP_RCTY (0x1 << 19)
503 #define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18)
504 #define BRIDGE_ISR_LLP_TCTY (0x1 << 17)
505 #define BRIDGE_ISR_SSRAM_PERR (0x1 << 16)
506 #define BRIDGE_ISR_PCI_ABORT (0x1 << 15)
507 #define BRIDGE_ISR_PCI_PARITY (0x1 << 14)
508 #define BRIDGE_ISR_PCI_SERR (0x1 << 13)
509 #define BRIDGE_ISR_PCI_PERR (0x1 << 12)
510 #define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11)
512 #define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10)
513 #define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9)
514 #define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8)
515 #define BRIDGE_ISR_INT_MSK (0xff << 0)
516 #define BRIDGE_ISR_INT(x) (0x1 << (x))
583 #define BRIDGE_IRR_MULTI_CLR (0x1 << 6)
584 #define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5)
585 #define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)
586 #define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3)
587 #define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2)
588 #define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1)
589 #define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0)
590 #define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0)
591 #define BRIDGE_IRR_ALL_CLR 0x7f
621 #define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n))
625 #define BRIDGE_INT_ADDR_HOST 0x0003FF00
626 #define BRIDGE_INT_ADDR_FLD 0x000000FF
628 #define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000
629 #define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000
630 #define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff
632 #define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff
645 #define BRIDGE_INT_ADDR_DEST_MEM 0
649 #define BRIDGE_DEV_ERR_LOCK_EN 0x10000000
650 #define BRIDGE_DEV_PAGE_CHK_DIS 0x08000000
651 #define BRIDGE_DEV_FORCE_PCI_PAR 0x04000000
652 #define BRIDGE_DEV_VIRTUAL_EN 0x02000000
653 #define BRIDGE_DEV_PMU_WRGA_EN 0x01000000
654 #define BRIDGE_DEV_DIR_WRGA_EN 0x00800000
655 #define BRIDGE_DEV_DEV_SIZE 0x00400000
656 #define BRIDGE_DEV_RT 0x00200000
657 #define BRIDGE_DEV_SWAP_PMU 0x00100000
658 #define BRIDGE_DEV_SWAP_DIR 0x00080000
659 #define BRIDGE_DEV_PREF 0x00040000
660 #define BRIDGE_DEV_PRECISE 0x00020000
661 #define BRIDGE_DEV_COH 0x00010000
662 #define BRIDGE_DEV_BARRIER 0x00008000
663 #define BRIDGE_DEV_GBR 0x00004000
664 #define BRIDGE_DEV_DEV_SWAP 0x00002000
665 #define BRIDGE_DEV_DEV_IO_MEM 0x00001000
666 #define BRIDGE_DEV_OFF_MASK 0x00000fff
683 #define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20) /* Device was master */
684 #define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19) /* Virtual Req value */
686 #define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
687 #define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
688 #define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF)
691 #define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x))
697 #define BRIDGE_RRB_EN 0x8 /* after shifting down */
698 #define BRIDGE_RRB_DEV 0x7 /* after shifting down */
699 #define BRIDGE_RRB_VDEV 0x4 /* after shifting down */
700 #define BRIDGE_RRB_PDEV 0x3 /* after shifting down */
703 #define BRIDGE_RRB_VALID(r) (0x00010000<<(r))
704 #define BRIDGE_RRB_INUSE(r) (0x00000001<<(r))
707 #define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r))
711 #define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */
722 #define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L
723 #define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL
724 #define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L
725 #define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL
726 #define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L
727 #define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL
730 #define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000 /* 1G PCI memory space */
731 #define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff
732 #define BRIDGE_MIN_PIO_ADDR_IO 0x00000000 /* 4G PCI IO space */
733 #define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff
747 #define BRIDGE_LOCAL_BASE 0
748 #define BRIDGE_DMA_MAPPED_BASE 0x40000000
749 #define BRIDGE_DMA_MAPPED_SIZE 0x40000000 /* 1G Bytes */
750 #define BRIDGE_DMA_DIRECT_BASE 0x80000000
751 #define BRIDGE_DMA_DIRECT_SIZE 0x80000000 /* 2G Bytes */
794 #define PCI64_ATTR_TARG_MASK 0xf000000000000000
796 #define PCI64_ATTR_PREF 0x0800000000000000
797 #define PCI64_ATTR_PREC 0x0400000000000000
798 #define PCI64_ATTR_VIRTUAL 0x0200000000000000
799 #define PCI64_ATTR_BAR 0x0100000000000000
800 #define PCI64_ATTR_RMF_MASK 0x00ff000000000000