Lines Matching +full:block +full:- +full:fetch

7  * Copyright (c) 2003-2008 Cavium Networks
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
35 #include <asm/octeon/octeon-model.h>
54  * errata Core-401. This can cause a single syncw to not enforce
87  * CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable
90  * unpredictable, but may also change again - up until the point when one
98  * its dirty bit for a block. Basically, SW is telling HW that the
99  * current version of the block will not be used.
120 /* fetch and lock the state. */
124 /* invalidate the cache block and clear the USED bits for the block */
126 /* load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register */
134 /* some new cop0-like stuff */