Lines Matching +full:0 +full:x41800000
19 #define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1)
20 #define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val)
22 #define read_c0_mvpconf0() __read_32bit_c0_register($0, 2)
23 #define read_c0_mvpconf1() __read_32bit_c0_register($0, 3)
49 #define CP0_MVPCONTROL $0, 1
50 #define CP0_MVPCONF0 $0, 2
51 #define CP0_MVPCONF1 $0, 3
84 #define MVPCONF0_PTC_SHIFT 0
85 #define MVPCONF0_PTC ( _ULCAST_(0xff))
87 #define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
91 #define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
95 #define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
104 #define VPECONTROL_TARGTC (_ULCAST_(0xff))
109 #define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
112 #define THREX_TU 0
125 #define VPECONF0_VPA_SHIFT 0
130 #define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
133 #define VPECONF1_NCP1_SHIFT 0
134 #define VPECONF1_NCP1 (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT)
136 #define VPECONF1_NCP2 (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT)
138 #define VPECONF1_NCX (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT)
141 #define TCSTATUS_TASID (_ULCAST_(0xff))
159 #define TC_RUNNING 0
169 #define TCBIND_CURVPE_SHIFT 0
170 #define TCBIND_CURVPE (_ULCAST_(0xf))
174 #define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
194 _ASM_INSN_IF_MIPS(0x41600001 | __rt << 16) \
195 _ASM_INSN32_IF_MM(0x0000157C | __rt << 21))
200 int res = 0; in dvpe()
206 " dvpe %0 \n" in dvpe()
219 _ASM_INSN_IF_MIPS(0x41600021 | __rt << 16) \
220 _ASM_INSN32_IF_MM(0x0000357C | __rt << 21))
229 " evpe $0 \n" in __raw_evpe()
248 _ASM_INSN_IF_MIPS(0x41600bc1 | __rt << 16) \
249 _ASM_INSN32_IF_MM(0x0000057C | __rt << 21))
260 " dmt %0 \n" in dmt()
273 _ASM_INSN_IF_MIPS(0x41600be1 | __rt << 16) \
274 _ASM_INSN32_IF_MM(0x0000257C | __rt << 21))
283 " emt $0 \n" in __raw_emt()
311 _ASM_INSN_IF_MIPS(0x41000000 | __rt << 16 | \
313 _ASM_INSN32_IF_MM(0x0000000E | __rt << 21 | \
325 " mftc0 %0, " #rt ", " #sel " \n" \
335 _ASM_INSN_IF_MIPS(0x41000020 | __rt << 16 | \
337 _ASM_INSN32_IF_MM(0x0000040E | __rt << 21 | \
349 " mftgpr %0," #rt " \n" \
362 " mftr %0, " #rt ", " #u ", " #sel " \n" \
370 _ASM_INSN_IF_MIPS(0x41800020 | __rt << 16 | \
372 _ASM_INSN32_IF_MM(0x00000406 | __rt << 21 | \
382 " mttgpr %0, " #rs " \n" \
386 } while (0)
390 _ASM_INSN_IF_MIPS(0x41800000 | __rt << 16 | \
392 _ASM_INSN32_IF_MM(0x0000040E | __rt << 21 | \
402 " mttc0 %0," #rs ", " #sel " \n" \
413 "mttr %0," #rd ", " #u ", " #sel \
422 } while (0)
432 #define read_vpe_c0_count() mftc0($9, 0)
433 #define write_vpe_c0_count(val) mttc0($9, 0, val)
434 #define read_vpe_c0_status() mftc0($12, 0)
435 #define write_vpe_c0_status(val) mttc0($12, 0, val)
436 #define read_vpe_c0_cause() mftc0($13, 0)
437 #define write_vpe_c0_cause(val) mttc0($13, 0, val)
438 #define read_vpe_c0_config() mftc0($16, 0)
439 #define write_vpe_c0_config(val) mttc0($16, 0, val)
446 #define write_vpe_c0_compare(val) mttc0($11, 0, val)
447 #define read_vpe_c0_badvaddr() mftc0($8, 0)
448 #define read_vpe_c0_epc() mftc0($14, 0)
449 #define write_vpe_c0_epc(val) mttc0($14, 0, val)