Lines Matching +full:64 +full:bit

52  * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
53  * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
58  * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
143 GCR_ACCESSOR_RO(64, 0x000, config)
151 GCR_ACCESSOR_RW(64, 0x008, base)
179 #define CM_GCR_ERR_CONTROL_L2_ECC_EN		BIT(1)
180 #define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT	BIT(0)
183 GCR_ACCESSOR_RW(64, 0x040, error_mask)
186 GCR_ACCESSOR_RW(64, 0x048, error_cause)
192 GCR_ACCESSOR_RW(64, 0x050, error_addr)
195 GCR_ACCESSOR_RW(64, 0x058, error_mult)
199 GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
201 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN		BIT(0)
204 GCR_ACCESSOR_RW(64, 0x080, gic_base)
206 #define CM_GCR_GIC_BASE_GICEN			BIT(0)
209 GCR_ACCESSOR_RW(64, 0x088, cpc_base)
211 #define CM_GCR_CPC_BASE_CPCEN			BIT(0)
214 GCR_ACCESSOR_RW(64, 0x090, reg0_base)
215 GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
216 GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
217 GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
221 GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
222 GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
223 GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
224 GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
227 #define CM_GCR_REGn_MASK_CCAOVREN		BIT(4)
228 #define CM_GCR_REGn_MASK_DROPL2			BIT(2)
237 #define CM_GCR_GIC_STATUS_EX			BIT(0)
241 #define CM_GCR_CPC_STATUS_EX			BIT(0)
249 #define CM_GCR_L2_CONFIG_BYPASS			BIT(20)
261 #define CM_GCR_L2_PFT_CONTROL_PFTEN		BIT(8)
266 #define CM_GCR_L2_PFT_CONTROL_B_CEN		BIT(8)
271 #define CM_GCR_L2SM_COP_PRESENT			BIT(31)
278 #define CM_GCR_L2SM_COP_RUNNING			BIT(5)
292 GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
297 GCR_ACCESSOR_RW(64, 0x680, bev_base)
305 #define CM3_GCR_Cx_COHERENCE_COHEN		BIT(0)
315 #define CM_GCR_Cx_OTHER_CLUSTER_EN		BIT(31)		/* CM >= 3.5 */
316 #define CM_GCR_Cx_OTHER_GIC_EN			BIT(30)		/* CM >= 3.5 */
330 #define CM_GCR_Cx_RESET_BASE_MODE		BIT(1)
339 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET	BIT(31)
340 #define CM_GCR_Cx_RESET_EXT_BASE_UEB		BIT(30)
343 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT	BIT(0)