Lines Matching +full:0 +full:x1e000000
51 for (x = 0; x < 100000; x++) \
60 #define LOONGSON_FLASH_BASE 0x1c000000
61 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
64 #define LOONGSON_LIO0_BASE 0x1e000000
65 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
68 #define LOONGSON_BOOT_BASE 0x1fc00000
69 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
71 #define LOONGSON_REG_BASE 0x1fe00000
72 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
75 #define LOONGSON_LIO1_BASE 0x1ff00000
76 #define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
79 #define LOONGSON_PCILO0_BASE 0x10000000
80 #define LOONGSON_PCILO1_BASE 0x14000000
81 #define LOONGSON_PCILO2_BASE 0x18000000
83 #define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
86 #define LOONGSON_PCICFG_BASE 0x1fe80000
87 #define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
89 #define LOONGSON_PCIIO_BASE 0x1fd00000
91 #define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
96 #define LOONGSON_PCICONFIGBASE 0x00
97 #define LOONGSON_REGBASE 0x100
102 #define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
103 #define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
104 #define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
105 #define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
106 #define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
107 #define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
108 #define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
109 #define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
110 #define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
111 #define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
112 #define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
114 #define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
116 #define LOONGSON_PCICMD_PERR_CLR 0x80000000
117 #define LOONGSON_PCICMD_SERR_CLR 0x40000000
118 #define LOONGSON_PCICMD_MABORT_CLR 0x20000000
119 #define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
120 #define LOONGSON_PCICMD_TABORT_CLR 0x08000000
121 #define LOONGSON_PCICMD_MPERR_CLR 0x01000000
122 #define LOONGSON_PCICMD_PERRRESPEN 0x00000040
123 #define LOONGSON_PCICMD_ASTEPEN 0x00000080
124 #define LOONGSON_PCICMD_SERREN 0x00000100
125 #define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
130 #define LOONGSON_GENCFG_OFFSET 0x4
133 #define LOONGSON_GENCFG_DEBUGMODE 0x00000001
134 #define LOONGSON_GENCFG_SNOOPEN 0x00000002
135 #define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
137 #define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
138 #define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
139 #define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
140 #define LOONGSON_GENCFG_BYTESWAP 0x00000040
142 #define LOONGSON_GENCFG_UNCACHED 0x00000080
143 #define LOONGSON_GENCFG_PREFETCHEN 0x00000100
144 #define LOONGSON_GENCFG_WBEHINDEN 0x00000200
145 #define LOONGSON_GENCFG_CACHEALG 0x00000c00
147 #define LOONGSON_GENCFG_PCIQUEUE 0x00001000
148 #define LOONGSON_GENCFG_CACHESTOP 0x00002000
149 #define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
150 #define LOONGSON_GENCFG_BUSERREN 0x00008000
151 #define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
152 #define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
156 #define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
157 #define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
158 #define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
162 #define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
163 #define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
167 #define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
168 #define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
169 #define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
173 #define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
174 #define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
175 #define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
176 #define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
179 #define LOONGSON_ICU_MBOXES 0x0000000f
180 #define LOONGSON_ICU_MBOXES_SHIFT 0
181 #define LOONGSON_ICU_DMARDY 0x00000010
182 #define LOONGSON_ICU_DMAEMPTY 0x00000020
183 #define LOONGSON_ICU_COPYRDY 0x00000040
184 #define LOONGSON_ICU_COPYEMPTY 0x00000080
185 #define LOONGSON_ICU_COPYERR 0x00000100
186 #define LOONGSON_ICU_PCIIRQ 0x00000200
187 #define LOONGSON_ICU_MASTERERR 0x00000400
188 #define LOONGSON_ICU_SYSTEMERR 0x00000800
189 #define LOONGSON_ICU_DRAMPERR 0x00001000
190 #define LOONGSON_ICU_RETRYERR 0x00002000
191 #define LOONGSON_ICU_GPIOS 0x01ff0000
193 #define LOONGSON_ICU_GPINS 0x7e000000
201 #define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
202 #define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
203 #define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
204 #define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
208 #define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
209 #define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
210 #define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
211 #define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
212 #define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
213 #define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
217 #define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
218 #define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
221 #define LOONGSON_CHIPCFG (void __iomem *)TO_UNCAC(0x1fc00180)
225 #define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
226 #define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
227 #define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
229 #define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
231 #define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
249 #define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
250 #define LOONGSON_ADDRWINCFG_SIZE 0x180
256 #define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
257 #define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
258 #define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
259 #define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
261 #define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
262 #define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
263 #define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
264 #define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
266 #define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
267 #define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
268 #define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
269 #define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
271 #define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
272 #define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
273 #define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
274 #define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
276 #define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
277 #define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
278 #define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
279 #define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
281 #define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
282 #define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
283 #define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
284 #define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
286 #define ADDRWIN_WIN0 0
291 #define ADDRWIN_MAP_DST_DDR 0
298 * win: 0, 1, 2, 3
307 } while (0)