Lines Matching +full:0 +full:xfffe0080
13 #define BCM3368_CPU_ID 0x3368
14 #define BCM6328_CPU_ID 0x6328
15 #define BCM6338_CPU_ID 0x6338
16 #define BCM6345_CPU_ID 0x6345
17 #define BCM6348_CPU_ID 0x6348
18 #define BCM6358_CPU_ID 0x6358
19 #define BCM6362_CPU_ID 0x6362
20 #define BCM6368_CPU_ID 0x6368
91 RSET_DSL_LMEM = 0,
166 #define BCM_3368_DSL_LMEM_BASE (0xdeadbeef)
167 #define BCM_3368_PERF_BASE (0xfff8c000)
168 #define BCM_3368_TIMER_BASE (0xfff8c040)
169 #define BCM_3368_WDT_BASE (0xfff8c080)
170 #define BCM_3368_UART0_BASE (0xfff8c100)
171 #define BCM_3368_UART1_BASE (0xfff8c120)
172 #define BCM_3368_GPIO_BASE (0xfff8c080)
173 #define BCM_3368_SPI_BASE (0xfff8c800)
174 #define BCM_3368_HSSPI_BASE (0xdeadbeef)
175 #define BCM_3368_UDC0_BASE (0xdeadbeef)
176 #define BCM_3368_USBDMA_BASE (0xdeadbeef)
177 #define BCM_3368_OHCI0_BASE (0xdeadbeef)
178 #define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef)
179 #define BCM_3368_USBH_PRIV_BASE (0xdeadbeef)
180 #define BCM_3368_USBD_BASE (0xdeadbeef)
181 #define BCM_3368_MPI_BASE (0xfff80000)
182 #define BCM_3368_PCMCIA_BASE (0xfff80054)
183 #define BCM_3368_PCIE_BASE (0xdeadbeef)
184 #define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef)
185 #define BCM_3368_DSL_BASE (0xdeadbeef)
186 #define BCM_3368_UBUS_BASE (0xdeadbeef)
187 #define BCM_3368_ENET0_BASE (0xfff98000)
188 #define BCM_3368_ENET1_BASE (0xfff98800)
189 #define BCM_3368_ENETDMA_BASE (0xfff99800)
190 #define BCM_3368_ENETDMAC_BASE (0xfff99900)
191 #define BCM_3368_ENETDMAS_BASE (0xfff99a00)
192 #define BCM_3368_ENETSW_BASE (0xdeadbeef)
193 #define BCM_3368_EHCI0_BASE (0xdeadbeef)
194 #define BCM_3368_SDRAM_BASE (0xdeadbeef)
195 #define BCM_3368_MEMC_BASE (0xfff84000)
196 #define BCM_3368_DDR_BASE (0xdeadbeef)
197 #define BCM_3368_M2M_BASE (0xdeadbeef)
198 #define BCM_3368_ATM_BASE (0xdeadbeef)
199 #define BCM_3368_XTM_BASE (0xdeadbeef)
200 #define BCM_3368_XTMDMA_BASE (0xdeadbeef)
201 #define BCM_3368_XTMDMAC_BASE (0xdeadbeef)
202 #define BCM_3368_XTMDMAS_BASE (0xdeadbeef)
203 #define BCM_3368_PCM_BASE (0xfff9c200)
204 #define BCM_3368_PCMDMA_BASE (0xdeadbeef)
205 #define BCM_3368_PCMDMAC_BASE (0xdeadbeef)
206 #define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
207 #define BCM_3368_RNG_BASE (0xdeadbeef)
208 #define BCM_3368_MISC_BASE (0xdeadbeef)
213 #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
214 #define BCM_6328_PERF_BASE (0xb0000000)
215 #define BCM_6328_TIMER_BASE (0xb0000040)
216 #define BCM_6328_WDT_BASE (0xb000005c)
217 #define BCM_6328_UART0_BASE (0xb0000100)
218 #define BCM_6328_UART1_BASE (0xb0000120)
219 #define BCM_6328_GPIO_BASE (0xb0000080)
220 #define BCM_6328_SPI_BASE (0xdeadbeef)
221 #define BCM_6328_HSSPI_BASE (0xb0001000)
222 #define BCM_6328_UDC0_BASE (0xdeadbeef)
223 #define BCM_6328_USBDMA_BASE (0xb000c000)
224 #define BCM_6328_OHCI0_BASE (0xb0002600)
225 #define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
226 #define BCM_6328_USBH_PRIV_BASE (0xb0002700)
227 #define BCM_6328_USBD_BASE (0xb0002400)
228 #define BCM_6328_MPI_BASE (0xdeadbeef)
229 #define BCM_6328_PCMCIA_BASE (0xdeadbeef)
230 #define BCM_6328_PCIE_BASE (0xb0e40000)
231 #define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
232 #define BCM_6328_DSL_BASE (0xb0001900)
233 #define BCM_6328_UBUS_BASE (0xdeadbeef)
234 #define BCM_6328_ENET0_BASE (0xdeadbeef)
235 #define BCM_6328_ENET1_BASE (0xdeadbeef)
236 #define BCM_6328_ENETDMA_BASE (0xb000d800)
237 #define BCM_6328_ENETDMAC_BASE (0xb000da00)
238 #define BCM_6328_ENETDMAS_BASE (0xb000dc00)
239 #define BCM_6328_ENETSW_BASE (0xb0e00000)
240 #define BCM_6328_EHCI0_BASE (0xb0002500)
241 #define BCM_6328_SDRAM_BASE (0xdeadbeef)
242 #define BCM_6328_MEMC_BASE (0xdeadbeef)
243 #define BCM_6328_DDR_BASE (0xb0003000)
244 #define BCM_6328_M2M_BASE (0xdeadbeef)
245 #define BCM_6328_ATM_BASE (0xdeadbeef)
246 #define BCM_6328_XTM_BASE (0xdeadbeef)
247 #define BCM_6328_XTMDMA_BASE (0xb000b800)
248 #define BCM_6328_XTMDMAC_BASE (0xdeadbeef)
249 #define BCM_6328_XTMDMAS_BASE (0xdeadbeef)
250 #define BCM_6328_PCM_BASE (0xb000a800)
251 #define BCM_6328_PCMDMA_BASE (0xdeadbeef)
252 #define BCM_6328_PCMDMAC_BASE (0xdeadbeef)
253 #define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
254 #define BCM_6328_RNG_BASE (0xdeadbeef)
255 #define BCM_6328_MISC_BASE (0xb0001800)
256 #define BCM_6328_OTP_BASE (0xb0000600)
261 #define BCM_6338_DSL_LMEM_BASE (0xfff00000)
262 #define BCM_6338_PERF_BASE (0xfffe0000)
263 #define BCM_6338_BB_BASE (0xfffe0100)
264 #define BCM_6338_TIMER_BASE (0xfffe0200)
265 #define BCM_6338_WDT_BASE (0xfffe021c)
266 #define BCM_6338_UART0_BASE (0xfffe0300)
267 #define BCM_6338_UART1_BASE (0xdeadbeef)
268 #define BCM_6338_GPIO_BASE (0xfffe0400)
269 #define BCM_6338_SPI_BASE (0xfffe0c00)
270 #define BCM_6338_HSSPI_BASE (0xdeadbeef)
271 #define BCM_6338_UDC0_BASE (0xdeadbeef)
272 #define BCM_6338_USBDMA_BASE (0xfffe2400)
273 #define BCM_6338_OHCI0_BASE (0xdeadbeef)
274 #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
275 #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
276 #define BCM_6338_USBD_BASE (0xdeadbeef)
277 #define BCM_6338_MPI_BASE (0xfffe3160)
278 #define BCM_6338_PCMCIA_BASE (0xdeadbeef)
279 #define BCM_6338_PCIE_BASE (0xdeadbeef)
280 #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
281 #define BCM_6338_DSL_BASE (0xfffe1000)
282 #define BCM_6338_UBUS_BASE (0xdeadbeef)
283 #define BCM_6338_ENET0_BASE (0xfffe2800)
284 #define BCM_6338_ENET1_BASE (0xdeadbeef)
285 #define BCM_6338_ENETDMA_BASE (0xfffe2400)
286 #define BCM_6338_ENETDMAC_BASE (0xfffe2500)
287 #define BCM_6338_ENETDMAS_BASE (0xfffe2600)
288 #define BCM_6338_ENETSW_BASE (0xdeadbeef)
289 #define BCM_6338_EHCI0_BASE (0xdeadbeef)
290 #define BCM_6338_SDRAM_BASE (0xfffe3100)
291 #define BCM_6338_MEMC_BASE (0xdeadbeef)
292 #define BCM_6338_DDR_BASE (0xdeadbeef)
293 #define BCM_6338_M2M_BASE (0xdeadbeef)
294 #define BCM_6338_ATM_BASE (0xfffe2000)
295 #define BCM_6338_XTM_BASE (0xdeadbeef)
296 #define BCM_6338_XTMDMA_BASE (0xdeadbeef)
297 #define BCM_6338_XTMDMAC_BASE (0xdeadbeef)
298 #define BCM_6338_XTMDMAS_BASE (0xdeadbeef)
299 #define BCM_6338_PCM_BASE (0xdeadbeef)
300 #define BCM_6338_PCMDMA_BASE (0xdeadbeef)
301 #define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
302 #define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
303 #define BCM_6338_RNG_BASE (0xdeadbeef)
304 #define BCM_6338_MISC_BASE (0xdeadbeef)
309 #define BCM_6345_DSL_LMEM_BASE (0xfff00000)
310 #define BCM_6345_PERF_BASE (0xfffe0000)
311 #define BCM_6345_BB_BASE (0xfffe0100)
312 #define BCM_6345_TIMER_BASE (0xfffe0200)
313 #define BCM_6345_WDT_BASE (0xfffe021c)
314 #define BCM_6345_UART0_BASE (0xfffe0300)
315 #define BCM_6345_UART1_BASE (0xdeadbeef)
316 #define BCM_6345_GPIO_BASE (0xfffe0400)
317 #define BCM_6345_SPI_BASE (0xdeadbeef)
318 #define BCM_6345_HSSPI_BASE (0xdeadbeef)
319 #define BCM_6345_UDC0_BASE (0xdeadbeef)
320 #define BCM_6345_USBDMA_BASE (0xfffe2800)
321 #define BCM_6345_ENET0_BASE (0xfffe1800)
322 #define BCM_6345_ENETDMA_BASE (0xfffe2800)
323 #define BCM_6345_ENETDMAC_BASE (0xfffe2840)
324 #define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
325 #define BCM_6345_ENETSW_BASE (0xdeadbeef)
326 #define BCM_6345_PCMCIA_BASE (0xfffe2028)
327 #define BCM_6345_MPI_BASE (0xfffe2000)
328 #define BCM_6345_PCIE_BASE (0xdeadbeef)
329 #define BCM_6345_OHCI0_BASE (0xfffe2100)
330 #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
331 #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
332 #define BCM_6345_USBD_BASE (0xdeadbeef)
333 #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
334 #define BCM_6345_DSL_BASE (0xdeadbeef)
335 #define BCM_6345_UBUS_BASE (0xdeadbeef)
336 #define BCM_6345_ENET1_BASE (0xdeadbeef)
337 #define BCM_6345_EHCI0_BASE (0xdeadbeef)
338 #define BCM_6345_SDRAM_BASE (0xfffe2300)
339 #define BCM_6345_MEMC_BASE (0xdeadbeef)
340 #define BCM_6345_DDR_BASE (0xdeadbeef)
341 #define BCM_6345_M2M_BASE (0xdeadbeef)
342 #define BCM_6345_ATM_BASE (0xfffe4000)
343 #define BCM_6345_XTM_BASE (0xdeadbeef)
344 #define BCM_6345_XTMDMA_BASE (0xdeadbeef)
345 #define BCM_6345_XTMDMAC_BASE (0xdeadbeef)
346 #define BCM_6345_XTMDMAS_BASE (0xdeadbeef)
347 #define BCM_6345_PCM_BASE (0xdeadbeef)
348 #define BCM_6345_PCMDMA_BASE (0xdeadbeef)
349 #define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
350 #define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
351 #define BCM_6345_RNG_BASE (0xdeadbeef)
352 #define BCM_6345_MISC_BASE (0xdeadbeef)
357 #define BCM_6348_DSL_LMEM_BASE (0xfff00000)
358 #define BCM_6348_PERF_BASE (0xfffe0000)
359 #define BCM_6348_TIMER_BASE (0xfffe0200)
360 #define BCM_6348_WDT_BASE (0xfffe021c)
361 #define BCM_6348_UART0_BASE (0xfffe0300)
362 #define BCM_6348_UART1_BASE (0xdeadbeef)
363 #define BCM_6348_GPIO_BASE (0xfffe0400)
364 #define BCM_6348_SPI_BASE (0xfffe0c00)
365 #define BCM_6348_HSSPI_BASE (0xdeadbeef)
366 #define BCM_6348_UDC0_BASE (0xfffe1000)
367 #define BCM_6348_USBDMA_BASE (0xdeadbeef)
368 #define BCM_6348_OHCI0_BASE (0xfffe1b00)
369 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
370 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
371 #define BCM_6348_USBD_BASE (0xdeadbeef)
372 #define BCM_6348_MPI_BASE (0xfffe2000)
373 #define BCM_6348_PCMCIA_BASE (0xfffe2054)
374 #define BCM_6348_PCIE_BASE (0xdeadbeef)
375 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
376 #define BCM_6348_M2M_BASE (0xfffe2800)
377 #define BCM_6348_DSL_BASE (0xfffe3000)
378 #define BCM_6348_ENET0_BASE (0xfffe6000)
379 #define BCM_6348_ENET1_BASE (0xfffe6800)
380 #define BCM_6348_ENETDMA_BASE (0xfffe7000)
381 #define BCM_6348_ENETDMAC_BASE (0xfffe7100)
382 #define BCM_6348_ENETDMAS_BASE (0xfffe7200)
383 #define BCM_6348_ENETSW_BASE (0xdeadbeef)
384 #define BCM_6348_EHCI0_BASE (0xdeadbeef)
385 #define BCM_6348_SDRAM_BASE (0xfffe2300)
386 #define BCM_6348_MEMC_BASE (0xdeadbeef)
387 #define BCM_6348_DDR_BASE (0xdeadbeef)
388 #define BCM_6348_ATM_BASE (0xfffe4000)
389 #define BCM_6348_XTM_BASE (0xdeadbeef)
390 #define BCM_6348_XTMDMA_BASE (0xdeadbeef)
391 #define BCM_6348_XTMDMAC_BASE (0xdeadbeef)
392 #define BCM_6348_XTMDMAS_BASE (0xdeadbeef)
393 #define BCM_6348_PCM_BASE (0xdeadbeef)
394 #define BCM_6348_PCMDMA_BASE (0xdeadbeef)
395 #define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
396 #define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
397 #define BCM_6348_RNG_BASE (0xdeadbeef)
398 #define BCM_6348_MISC_BASE (0xdeadbeef)
403 #define BCM_6358_DSL_LMEM_BASE (0xfff00000)
404 #define BCM_6358_PERF_BASE (0xfffe0000)
405 #define BCM_6358_TIMER_BASE (0xfffe0040)
406 #define BCM_6358_WDT_BASE (0xfffe005c)
407 #define BCM_6358_UART0_BASE (0xfffe0100)
408 #define BCM_6358_UART1_BASE (0xfffe0120)
409 #define BCM_6358_GPIO_BASE (0xfffe0080)
410 #define BCM_6358_SPI_BASE (0xfffe0800)
411 #define BCM_6358_HSSPI_BASE (0xdeadbeef)
412 #define BCM_6358_UDC0_BASE (0xfffe0800)
413 #define BCM_6358_USBDMA_BASE (0xdeadbeef)
414 #define BCM_6358_OHCI0_BASE (0xfffe1400)
415 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
416 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
417 #define BCM_6358_USBD_BASE (0xdeadbeef)
418 #define BCM_6358_MPI_BASE (0xfffe1000)
419 #define BCM_6358_PCMCIA_BASE (0xfffe1054)
420 #define BCM_6358_PCIE_BASE (0xdeadbeef)
421 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
422 #define BCM_6358_M2M_BASE (0xdeadbeef)
423 #define BCM_6358_DSL_BASE (0xfffe3000)
424 #define BCM_6358_ENET0_BASE (0xfffe4000)
425 #define BCM_6358_ENET1_BASE (0xfffe4800)
426 #define BCM_6358_ENETDMA_BASE (0xfffe5000)
427 #define BCM_6358_ENETDMAC_BASE (0xfffe5100)
428 #define BCM_6358_ENETDMAS_BASE (0xfffe5200)
429 #define BCM_6358_ENETSW_BASE (0xdeadbeef)
430 #define BCM_6358_EHCI0_BASE (0xfffe1300)
431 #define BCM_6358_SDRAM_BASE (0xdeadbeef)
432 #define BCM_6358_MEMC_BASE (0xfffe1200)
433 #define BCM_6358_DDR_BASE (0xfffe12a0)
434 #define BCM_6358_ATM_BASE (0xfffe2000)
435 #define BCM_6358_XTM_BASE (0xdeadbeef)
436 #define BCM_6358_XTMDMA_BASE (0xdeadbeef)
437 #define BCM_6358_XTMDMAC_BASE (0xdeadbeef)
438 #define BCM_6358_XTMDMAS_BASE (0xdeadbeef)
439 #define BCM_6358_PCM_BASE (0xfffe1600)
440 #define BCM_6358_PCMDMA_BASE (0xfffe1800)
441 #define BCM_6358_PCMDMAC_BASE (0xfffe1900)
442 #define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
443 #define BCM_6358_RNG_BASE (0xdeadbeef)
444 #define BCM_6358_MISC_BASE (0xdeadbeef)
450 #define BCM_6362_DSL_LMEM_BASE (0xdeadbeef)
451 #define BCM_6362_PERF_BASE (0xb0000000)
452 #define BCM_6362_TIMER_BASE (0xb0000040)
453 #define BCM_6362_WDT_BASE (0xb000005c)
454 #define BCM_6362_UART0_BASE (0xb0000100)
455 #define BCM_6362_UART1_BASE (0xb0000120)
456 #define BCM_6362_GPIO_BASE (0xb0000080)
457 #define BCM_6362_SPI_BASE (0xb0000800)
458 #define BCM_6362_HSSPI_BASE (0xb0001000)
459 #define BCM_6362_UDC0_BASE (0xdeadbeef)
460 #define BCM_6362_USBDMA_BASE (0xb000c000)
461 #define BCM_6362_OHCI0_BASE (0xb0002600)
462 #define BCM_6362_OHCI_PRIV_BASE (0xdeadbeef)
463 #define BCM_6362_USBH_PRIV_BASE (0xb0002700)
464 #define BCM_6362_USBD_BASE (0xb0002400)
465 #define BCM_6362_MPI_BASE (0xdeadbeef)
466 #define BCM_6362_PCMCIA_BASE (0xdeadbeef)
467 #define BCM_6362_PCIE_BASE (0xb0e40000)
468 #define BCM_6362_SDRAM_REGS_BASE (0xdeadbeef)
469 #define BCM_6362_DSL_BASE (0xdeadbeef)
470 #define BCM_6362_UBUS_BASE (0xdeadbeef)
471 #define BCM_6362_ENET0_BASE (0xdeadbeef)
472 #define BCM_6362_ENET1_BASE (0xdeadbeef)
473 #define BCM_6362_ENETDMA_BASE (0xb000d800)
474 #define BCM_6362_ENETDMAC_BASE (0xb000da00)
475 #define BCM_6362_ENETDMAS_BASE (0xb000dc00)
476 #define BCM_6362_ENETSW_BASE (0xb0e00000)
477 #define BCM_6362_EHCI0_BASE (0xb0002500)
478 #define BCM_6362_SDRAM_BASE (0xdeadbeef)
479 #define BCM_6362_MEMC_BASE (0xdeadbeef)
480 #define BCM_6362_DDR_BASE (0xb0003000)
481 #define BCM_6362_M2M_BASE (0xdeadbeef)
482 #define BCM_6362_ATM_BASE (0xdeadbeef)
483 #define BCM_6362_XTM_BASE (0xb0007800)
484 #define BCM_6362_XTMDMA_BASE (0xb000b800)
485 #define BCM_6362_XTMDMAC_BASE (0xdeadbeef)
486 #define BCM_6362_XTMDMAS_BASE (0xdeadbeef)
487 #define BCM_6362_PCM_BASE (0xb000a800)
488 #define BCM_6362_PCMDMA_BASE (0xdeadbeef)
489 #define BCM_6362_PCMDMAC_BASE (0xdeadbeef)
490 #define BCM_6362_PCMDMAS_BASE (0xdeadbeef)
491 #define BCM_6362_RNG_BASE (0xdeadbeef)
492 #define BCM_6362_MISC_BASE (0xb0001800)
494 #define BCM_6362_NAND_REG_BASE (0xb0000200)
495 #define BCM_6362_NAND_CACHE_BASE (0xb0000600)
496 #define BCM_6362_LED_BASE (0xb0001900)
497 #define BCM_6362_IPSEC_BASE (0xb0002800)
498 #define BCM_6362_IPSEC_DMA_BASE (0xb000d000)
499 #define BCM_6362_WLAN_CHIPCOMMON_BASE (0xb0004000)
500 #define BCM_6362_WLAN_D11_BASE (0xb0005000)
501 #define BCM_6362_WLAN_SHIM_BASE (0xb0007000)
506 #define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
507 #define BCM_6368_PERF_BASE (0xb0000000)
508 #define BCM_6368_TIMER_BASE (0xb0000040)
509 #define BCM_6368_WDT_BASE (0xb000005c)
510 #define BCM_6368_UART0_BASE (0xb0000100)
511 #define BCM_6368_UART1_BASE (0xb0000120)
512 #define BCM_6368_GPIO_BASE (0xb0000080)
513 #define BCM_6368_SPI_BASE (0xb0000800)
514 #define BCM_6368_HSSPI_BASE (0xdeadbeef)
515 #define BCM_6368_UDC0_BASE (0xdeadbeef)
516 #define BCM_6368_USBDMA_BASE (0xb0004800)
517 #define BCM_6368_OHCI0_BASE (0xb0001600)
518 #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
519 #define BCM_6368_USBH_PRIV_BASE (0xb0001700)
520 #define BCM_6368_USBD_BASE (0xb0001400)
521 #define BCM_6368_MPI_BASE (0xb0001000)
522 #define BCM_6368_PCMCIA_BASE (0xb0001054)
523 #define BCM_6368_PCIE_BASE (0xdeadbeef)
524 #define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
525 #define BCM_6368_M2M_BASE (0xdeadbeef)
526 #define BCM_6368_DSL_BASE (0xdeadbeef)
527 #define BCM_6368_ENET0_BASE (0xdeadbeef)
528 #define BCM_6368_ENET1_BASE (0xdeadbeef)
529 #define BCM_6368_ENETDMA_BASE (0xb0006800)
530 #define BCM_6368_ENETDMAC_BASE (0xb0006a00)
531 #define BCM_6368_ENETDMAS_BASE (0xb0006c00)
532 #define BCM_6368_ENETSW_BASE (0xb0f00000)
533 #define BCM_6368_EHCI0_BASE (0xb0001500)
534 #define BCM_6368_SDRAM_BASE (0xdeadbeef)
535 #define BCM_6368_MEMC_BASE (0xb0001200)
536 #define BCM_6368_DDR_BASE (0xb0001280)
537 #define BCM_6368_ATM_BASE (0xdeadbeef)
538 #define BCM_6368_XTM_BASE (0xb0001800)
539 #define BCM_6368_XTMDMA_BASE (0xb0005000)
540 #define BCM_6368_XTMDMAC_BASE (0xb0005200)
541 #define BCM_6368_XTMDMAS_BASE (0xb0005400)
542 #define BCM_6368_PCM_BASE (0xb0004000)
543 #define BCM_6368_PCMDMA_BASE (0xb0005800)
544 #define BCM_6368_PCMDMAC_BASE (0xb0005a00)
545 #define BCM_6368_PCMDMAS_BASE (0xb0005c00)
546 #define BCM_6368_RNG_BASE (0xb0004180)
547 #define BCM_6368_MISC_BASE (0xdeadbeef)
605 IRQ_TIMER = 0,
645 #define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
649 #define BCM_3368_DSL_IRQ 0
650 #define BCM_3368_UDC0_IRQ 0
651 #define BCM_3368_OHCI0_IRQ 0
657 #define BCM_3368_HSSPI_IRQ 0
658 #define BCM_3368_EHCI0_IRQ 0
659 #define BCM_3368_USBD_IRQ 0
660 #define BCM_3368_USBD_RXDMA0_IRQ 0
661 #define BCM_3368_USBD_TXDMA0_IRQ 0
662 #define BCM_3368_USBD_RXDMA1_IRQ 0
663 #define BCM_3368_USBD_TXDMA1_IRQ 0
664 #define BCM_3368_USBD_RXDMA2_IRQ 0
665 #define BCM_3368_USBD_TXDMA2_IRQ 0
669 #define BCM_3368_PCMCIA_IRQ 0
670 #define BCM_3368_ATM_IRQ 0
671 #define BCM_3368_ENETSW_RXDMA0_IRQ 0
672 #define BCM_3368_ENETSW_RXDMA1_IRQ 0
673 #define BCM_3368_ENETSW_RXDMA2_IRQ 0
674 #define BCM_3368_ENETSW_RXDMA3_IRQ 0
675 #define BCM_3368_ENETSW_TXDMA0_IRQ 0
676 #define BCM_3368_ENETSW_TXDMA1_IRQ 0
677 #define BCM_3368_ENETSW_TXDMA2_IRQ 0
678 #define BCM_3368_ENETSW_TXDMA3_IRQ 0
679 #define BCM_3368_XTM_IRQ 0
680 #define BCM_3368_XTM_DMA0_IRQ 0
694 #define BCM_6328_SPI_IRQ 0
698 #define BCM_6328_UDC0_IRQ 0
699 #define BCM_6328_ENET0_IRQ 0
700 #define BCM_6328_ENET1_IRQ 0
712 #define BCM_6328_PCMCIA_IRQ 0
713 #define BCM_6328_ENET0_RXDMA_IRQ 0
714 #define BCM_6328_ENET0_TXDMA_IRQ 0
715 #define BCM_6328_ENET1_RXDMA_IRQ 0
716 #define BCM_6328_ENET1_TXDMA_IRQ 0
718 #define BCM_6328_ATM_IRQ 0
719 #define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)
723 #define BCM_6328_ENETSW_TXDMA0_IRQ 0
724 #define BCM_6328_ENETSW_TXDMA1_IRQ 0
725 #define BCM_6328_ENETSW_TXDMA2_IRQ 0
726 #define BCM_6328_ENETSW_TXDMA3_IRQ 0
740 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
743 #define BCM_6338_UART1_IRQ 0
746 #define BCM_6338_ENET1_IRQ 0
748 #define BCM_6338_HSSPI_IRQ 0
749 #define BCM_6338_OHCI0_IRQ 0
750 #define BCM_6338_EHCI0_IRQ 0
751 #define BCM_6338_USBD_IRQ 0
752 #define BCM_6338_USBD_RXDMA0_IRQ 0
753 #define BCM_6338_USBD_TXDMA0_IRQ 0
754 #define BCM_6338_USBD_RXDMA1_IRQ 0
755 #define BCM_6338_USBD_TXDMA1_IRQ 0
756 #define BCM_6338_USBD_RXDMA2_IRQ 0
757 #define BCM_6338_USBD_TXDMA2_IRQ 0
760 #define BCM_6338_ENET1_RXDMA_IRQ 0
761 #define BCM_6338_ENET1_TXDMA_IRQ 0
762 #define BCM_6338_PCI_IRQ 0
763 #define BCM_6338_PCMCIA_IRQ 0
764 #define BCM_6338_ATM_IRQ 0
765 #define BCM_6338_ENETSW_RXDMA0_IRQ 0
766 #define BCM_6338_ENETSW_RXDMA1_IRQ 0
767 #define BCM_6338_ENETSW_RXDMA2_IRQ 0
768 #define BCM_6338_ENETSW_RXDMA3_IRQ 0
769 #define BCM_6338_ENETSW_TXDMA0_IRQ 0
770 #define BCM_6338_ENETSW_TXDMA1_IRQ 0
771 #define BCM_6338_ENETSW_TXDMA2_IRQ 0
772 #define BCM_6338_ENETSW_TXDMA3_IRQ 0
773 #define BCM_6338_XTM_IRQ 0
774 #define BCM_6338_XTM_DMA0_IRQ 0
779 #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
780 #define BCM_6345_SPI_IRQ 0
782 #define BCM_6345_UART1_IRQ 0
785 #define BCM_6345_ENET1_IRQ 0
787 #define BCM_6345_HSSPI_IRQ 0
788 #define BCM_6345_OHCI0_IRQ 0
789 #define BCM_6345_EHCI0_IRQ 0
790 #define BCM_6345_USBD_IRQ 0
791 #define BCM_6345_USBD_RXDMA0_IRQ 0
792 #define BCM_6345_USBD_TXDMA0_IRQ 0
793 #define BCM_6345_USBD_RXDMA1_IRQ 0
794 #define BCM_6345_USBD_TXDMA1_IRQ 0
795 #define BCM_6345_USBD_RXDMA2_IRQ 0
796 #define BCM_6345_USBD_TXDMA2_IRQ 0
799 #define BCM_6345_ENET1_RXDMA_IRQ 0
800 #define BCM_6345_ENET1_TXDMA_IRQ 0
801 #define BCM_6345_PCI_IRQ 0
802 #define BCM_6345_PCMCIA_IRQ 0
803 #define BCM_6345_ATM_IRQ 0
804 #define BCM_6345_ENETSW_RXDMA0_IRQ 0
805 #define BCM_6345_ENETSW_RXDMA1_IRQ 0
806 #define BCM_6345_ENETSW_RXDMA2_IRQ 0
807 #define BCM_6345_ENETSW_RXDMA3_IRQ 0
808 #define BCM_6345_ENETSW_TXDMA0_IRQ 0
809 #define BCM_6345_ENETSW_TXDMA1_IRQ 0
810 #define BCM_6345_ENETSW_TXDMA2_IRQ 0
811 #define BCM_6345_ENETSW_TXDMA3_IRQ 0
812 #define BCM_6345_XTM_IRQ 0
813 #define BCM_6345_XTM_DMA0_IRQ 0
818 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
821 #define BCM_6348_UART1_IRQ 0
826 #define BCM_6348_HSSPI_IRQ 0
828 #define BCM_6348_EHCI0_IRQ 0
829 #define BCM_6348_USBD_IRQ 0
830 #define BCM_6348_USBD_RXDMA0_IRQ 0
831 #define BCM_6348_USBD_TXDMA0_IRQ 0
832 #define BCM_6348_USBD_RXDMA1_IRQ 0
833 #define BCM_6348_USBD_TXDMA1_IRQ 0
834 #define BCM_6348_USBD_RXDMA2_IRQ 0
835 #define BCM_6348_USBD_TXDMA2_IRQ 0
843 #define BCM_6348_ENETSW_RXDMA0_IRQ 0
844 #define BCM_6348_ENETSW_RXDMA1_IRQ 0
845 #define BCM_6348_ENETSW_RXDMA2_IRQ 0
846 #define BCM_6348_ENETSW_RXDMA3_IRQ 0
847 #define BCM_6348_ENETSW_TXDMA0_IRQ 0
848 #define BCM_6348_ENETSW_TXDMA1_IRQ 0
849 #define BCM_6348_ENETSW_TXDMA2_IRQ 0
850 #define BCM_6348_ENETSW_TXDMA3_IRQ 0
851 #define BCM_6348_XTM_IRQ 0
852 #define BCM_6348_XTM_DMA0_IRQ 0
857 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
865 #define BCM_6358_HSSPI_IRQ 0
868 #define BCM_6358_USBD_IRQ 0
869 #define BCM_6358_USBD_RXDMA0_IRQ 0
870 #define BCM_6358_USBD_TXDMA0_IRQ 0
871 #define BCM_6358_USBD_RXDMA1_IRQ 0
872 #define BCM_6358_USBD_TXDMA1_IRQ 0
873 #define BCM_6358_USBD_RXDMA2_IRQ 0
874 #define BCM_6358_USBD_TXDMA2_IRQ 0
882 #define BCM_6358_ENETSW_RXDMA0_IRQ 0
883 #define BCM_6358_ENETSW_RXDMA1_IRQ 0
884 #define BCM_6358_ENETSW_RXDMA2_IRQ 0
885 #define BCM_6358_ENETSW_RXDMA3_IRQ 0
886 #define BCM_6358_ENETSW_TXDMA0_IRQ 0
887 #define BCM_6358_ENETSW_TXDMA1_IRQ 0
888 #define BCM_6358_ENETSW_TXDMA2_IRQ 0
889 #define BCM_6358_ENETSW_TXDMA3_IRQ 0
890 #define BCM_6358_XTM_IRQ 0
891 #define BCM_6358_XTM_DMA0_IRQ 0
905 #define BCM_6362_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
910 #define BCM_6362_UDC0_IRQ 0
911 #define BCM_6362_ENET0_IRQ 0
912 #define BCM_6362_ENET1_IRQ 0
924 #define BCM_6362_PCMCIA_IRQ 0
925 #define BCM_6362_ENET0_RXDMA_IRQ 0
926 #define BCM_6362_ENET0_TXDMA_IRQ 0
927 #define BCM_6362_ENET1_RXDMA_IRQ 0
928 #define BCM_6362_ENET1_TXDMA_IRQ 0
930 #define BCM_6362_ATM_IRQ 0
931 #define BCM_6362_ENETSW_RXDMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 0)
935 #define BCM_6362_ENETSW_TXDMA0_IRQ 0
936 #define BCM_6362_ENETSW_TXDMA1_IRQ 0
937 #define BCM_6362_ENETSW_TXDMA2_IRQ 0
938 #define BCM_6362_ENETSW_TXDMA3_IRQ 0
939 #define BCM_6362_XTM_IRQ 0
970 #define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
975 #define BCM_6368_ENET0_IRQ 0
976 #define BCM_6368_ENET1_IRQ 0
978 #define BCM_6368_HSSPI_IRQ 0
988 #define BCM_6368_PCMCIA_IRQ 0
989 #define BCM_6368_ENET0_RXDMA_IRQ 0
990 #define BCM_6368_ENET0_TXDMA_IRQ 0
991 #define BCM_6368_ENET1_RXDMA_IRQ 0
992 #define BCM_6368_ENET1_TXDMA_IRQ 0
994 #define BCM_6368_ATM_IRQ 0
995 #define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)