15  * GPIO0-31 from GPIO1 block,	GPIO200-215 from GPIO2 block.
218 static inline void alchemy_gpio1_set_value(int gpio, int v)  in alchemy_gpio1_set_value()  argument
221 	unsigned long r = v ? AU1000_SYS_OUTPUTSET : AU1000_SYS_OUTPUTCLR;  in alchemy_gpio1_set_value()
238 static inline int alchemy_gpio1_direction_output(int gpio, int v)  in alchemy_gpio1_direction_output()  argument
243 	alchemy_gpio1_set_value(gpio, v);  in alchemy_gpio1_direction_output()
298 static inline void alchemy_gpio2_set_value(int gpio, int v)  in alchemy_gpio2_set_value()  argument
302 	mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);  in alchemy_gpio2_set_value()
323 static inline int alchemy_gpio2_direction_output(int gpio, int v)  in alchemy_gpio2_direction_output()  argument
326 	alchemy_gpio2_set_value(gpio, v);  in alchemy_gpio2_direction_output()
373  * @gpio2:	The GPIO2 pin to activate (200...215).
375  * GPIO208-215 have one shared interrupt line to the INTC.  They are
382  * NOTE: Calling this macro is only necessary for GPIO208-215; all other
391  * (200-215 by default). No sanity checks are made,
399 	/* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */  in alchemy_gpio2_enable_int()
413  * @gpio2:	The GPIO2 pin to activate (200...215).
423 	/* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */  in alchemy_gpio2_disable_int()
474 static inline int alchemy_gpio_direction_output(int gpio, int v)  in alchemy_gpio_direction_output()  argument
477 		alchemy_gpio2_direction_output(gpio, v) :  in alchemy_gpio_direction_output()
478 		alchemy_gpio1_direction_output(gpio, v);  in alchemy_gpio_direction_output()
488 static inline void alchemy_gpio_set_value(int gpio, int v)  in alchemy_gpio_set_value()  argument
491 		alchemy_gpio2_set_value(gpio, v);  in alchemy_gpio_set_value()
493 		alchemy_gpio1_set_value(gpio, v);  in alchemy_gpio_set_value()