Lines Matching full:30
71 #define PSC_AC97CFG_RT_MASK (3 << 30)
72 #define PSC_AC97CFG_RT_FIFO1 (0 << 30)
73 #define PSC_AC97CFG_RT_FIFO2 (1 << 30)
74 #define PSC_AC97CFG_RT_FIFO4 (2 << 30)
75 #define PSC_AC97CFG_RT_FIFO8 (3 << 30)
190 #define PSC_I2SCFG_RT_MASK (3 << 30)
191 #define PSC_I2SCFG_RT_FIFO1 (0 << 30)
192 #define PSC_I2SCFG_RT_FIFO2 (1 << 30)
193 #define PSC_I2SCFG_RT_FIFO4 (2 << 30)
194 #define PSC_I2SCFG_RT_FIFO8 (3 << 30)
286 #define PSC_SPICFG_RT_MASK (3 << 30)
287 #define PSC_SPICFG_RT_FIFO1 (0 << 30)
288 #define PSC_SPICFG_RT_FIFO2 (1 << 30)
289 #define PSC_SPICFG_RT_FIFO4 (2 << 30)
290 #define PSC_SPICFG_RT_FIFO8 (3 << 30)
372 #define PSC_SMBCFG_RT_MASK (3 << 30)
373 #define PSC_SMBCFG_RT_FIFO1 (0 << 30)
374 #define PSC_SMBCFG_RT_FIFO2 (1 << 30)
375 #define PSC_SMBCFG_RT_FIFO4 (2 << 30)
376 #define PSC_SMBCFG_RT_FIFO8 (3 << 30)
399 #define PSC_SMBMSK_DN (1 << 30)
435 #define PSC_SMBEVNT_DN (1 << 30)
458 #define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30)