Lines Matching +full:0 +full:x14004000
105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
117 #define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
118 #define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
119 #define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
120 #define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */
121 #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
122 #define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
123 #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
124 #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
125 #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
126 #define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */
127 #define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
128 #define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
129 #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
130 #define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
131 #define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
132 #define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
133 #define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
134 #define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
135 #define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
136 #define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
137 #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
138 #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
139 #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
140 #define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
141 #define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
142 #define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */
143 #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
144 #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
145 #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
146 #define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */
147 #define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
148 #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
149 #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
150 #define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */
151 #define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
152 #define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
153 #define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
154 #define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
155 #define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
156 #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
157 #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */
158 #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */
159 #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
160 #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
161 #define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */
162 #define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
163 #define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
164 #define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
165 #define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
166 #define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
167 #define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
168 #define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
169 #define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
170 #define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
171 #define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
172 #define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
173 #define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
174 #define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
175 #define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
176 #define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
177 #define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
178 #define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
179 #define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
180 #define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
181 #define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */
182 #define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
183 #define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
184 #define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
185 #define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
186 #define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */
187 #define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */
188 #define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */
195 * Registers are 128bits (0x10 bytes), divided into 4 "banks".
197 #define AU1300_GPIC_PINVAL 0x0000
198 #define AU1300_GPIC_PINVALCLR 0x0010
199 #define AU1300_GPIC_IPEND 0x0020
200 #define AU1300_GPIC_PRIENC 0x0030
201 #define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */
202 #define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */
203 #define AU1300_GPIC_DMASEL 0x0060
204 #define AU1300_GPIC_DEVSEL 0x0080
205 #define AU1300_GPIC_DEVCLR 0x0090
206 #define AU1300_GPIC_RSTVAL 0x00a0
208 #define AU1300_GPIC_PINCFG 0x1000
211 (1 << ((gpio) & 0x1f))
217 #define GPIC_CFG_PC_GPIN 0
228 #define GPIC_CFG_IC_OFF (0 << 4)
242 #define AU1000_MEM_SDMODE0 0x0000
243 #define AU1000_MEM_SDMODE1 0x0004
244 #define AU1000_MEM_SDMODE2 0x0008
245 #define AU1000_MEM_SDADDR0 0x000C
246 #define AU1000_MEM_SDADDR1 0x0010
247 #define AU1000_MEM_SDADDR2 0x0014
248 #define AU1000_MEM_SDREFCFG 0x0018
249 #define AU1000_MEM_SDPRECMD 0x001C
250 #define AU1000_MEM_SDAUTOREF 0x0020
251 #define AU1000_MEM_SDWRMD0 0x0024
252 #define AU1000_MEM_SDWRMD1 0x0028
253 #define AU1000_MEM_SDWRMD2 0x002C
254 #define AU1000_MEM_SDSLEEP 0x0030
255 #define AU1000_MEM_SDSMCKE 0x0034
268 #define MEM_SDMODE_TCL (7 << 0)
270 #define MEM_SDMODE_BS_2Bank (0 << 20)
272 #define MEM_SDMODE_RS_11Row (0 << 18)
276 #define MEM_SDMODE_CS_7Col (0 << 15)
287 #define MEM_SDMODE_TCL_N(N) ((N) << 0)
291 #define MEM_SDADDR_CSBA (0x03FF << 10)
292 #define MEM_SDADDR_CSMASK (0x03FF << 0)
293 #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
294 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
300 #define MEM_SDREFCFG_RE (0x1ffffff << 0)
306 #define AU1550_MEM_SDMODE0 0x0800
307 #define AU1550_MEM_SDMODE1 0x0808
308 #define AU1550_MEM_SDMODE2 0x0810
309 #define AU1550_MEM_SDADDR0 0x0820
310 #define AU1550_MEM_SDADDR1 0x0828
311 #define AU1550_MEM_SDADDR2 0x0830
312 #define AU1550_MEM_SDCONFIGA 0x0840
313 #define AU1550_MEM_SDCONFIGB 0x0848
314 #define AU1550_MEM_SDSTAT 0x0850
315 #define AU1550_MEM_SDERRADDR 0x0858
316 #define AU1550_MEM_SDSTRIDE0 0x0860
317 #define AU1550_MEM_SDSTRIDE1 0x0868
318 #define AU1550_MEM_SDSTRIDE2 0x0870
319 #define AU1550_MEM_SDWRMD0 0x0880
320 #define AU1550_MEM_SDWRMD1 0x0888
321 #define AU1550_MEM_SDWRMD2 0x0890
322 #define AU1550_MEM_SDPRECMD 0x08C0
323 #define AU1550_MEM_SDAUTOREF 0x08C8
324 #define AU1550_MEM_SDSREF 0x08D0
328 #define AU1000_MEM_STCFG0 0x000
329 #define AU1000_MEM_STTIME0 0x004
330 #define AU1000_MEM_STADDR0 0x008
331 #define AU1000_MEM_STCFG1 0x010
332 #define AU1000_MEM_STTIME1 0x014
333 #define AU1000_MEM_STADDR1 0x018
334 #define AU1000_MEM_STCFG2 0x020
335 #define AU1000_MEM_STTIME2 0x024
336 #define AU1000_MEM_STADDR2 0x028
337 #define AU1000_MEM_STCFG3 0x030
338 #define AU1000_MEM_STTIME3 0x034
339 #define AU1000_MEM_STADDR3 0x038
340 #define AU1000_MEM_STNDCTL 0x100
341 #define AU1000_MEM_STSTAT 0x104
343 #define MEM_STNAND_CMD 0x0
344 #define MEM_STNAND_ADDR 0x4
345 #define MEM_STNAND_DATA 0x20
348 /* Programmable Counters 0 and 1 */
349 #define AU1000_SYS_CNTRCTRL 0x14
368 # define SYS_CNTRL_C0S (1 << 0)
370 /* Programmable Counter 0 Registers */
371 #define AU1000_SYS_TOYTRIM 0x00
372 #define AU1000_SYS_TOYWRITE 0x04
373 #define AU1000_SYS_TOYMATCH0 0x08
374 #define AU1000_SYS_TOYMATCH1 0x0c
375 #define AU1000_SYS_TOYMATCH2 0x10
376 #define AU1000_SYS_TOYREAD 0x40
379 #define AU1000_SYS_RTCTRIM 0x44
380 #define AU1000_SYS_RTCWRITE 0x48
381 #define AU1000_SYS_RTCMATCH0 0x4c
382 #define AU1000_SYS_RTCMATCH1 0x50
383 #define AU1000_SYS_RTCMATCH2 0x54
384 #define AU1000_SYS_RTCREAD 0x58
388 #define AU1000_SYS_PINFUNC 0x2C
404 # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
414 # define SYS_PF_PSC2_AC97 0
415 # define SYS_PF_PSC2_SPI 0
420 # define SYS_PF_PSC3_AC97 0
421 # define SYS_PF_PSC3_SPI 0
458 #define AU1000_SYS_SCRATCH0 0x18
459 #define AU1000_SYS_SCRATCH1 0x1c
460 #define AU1000_SYS_WAKEMSK 0x34
461 #define AU1000_SYS_ENDIAN 0x38
462 #define AU1000_SYS_POWERCTRL 0x3c
463 #define AU1000_SYS_WAKESRC 0x5c
464 #define AU1000_SYS_SLPPWR 0x78
465 #define AU1000_SYS_SLEEP 0x7c
472 #define AU1000_SYS_FREQCTRL0 0x20
473 #define AU1000_SYS_FREQCTRL1 0x24
474 #define AU1000_SYS_CLKSRC 0x28
475 #define AU1000_SYS_CPUPLL 0x60
476 #define AU1000_SYS_AUXPLL 0x64
477 #define AU1300_SYS_AUXPLL2 0x68
490 #define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)
495 #define ALCHEMY_PCI_IOWIN_START 0x00001000
496 #define ALCHEMY_PCI_IOWIN_END 0x0000FFFF
500 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
501 #define IOPORT_RESOURCE_END 0xffffffff
502 #define IOMEM_RESOURCE_START 0x10000000
503 #define IOMEM_RESOURCE_END 0xfffffffffULL
508 #define IOPORT_RESOURCE_START 0x10000000
509 #define IOPORT_RESOURCE_END 0xffffffff
510 #define IOMEM_RESOURCE_START 0x10000000
511 #define IOMEM_RESOURCE_END 0xfffffffffULL
516 #define PCI_REG_CMEM 0x0000
517 #define PCI_REG_CONFIG 0x0004
518 #define PCI_REG_B2BMASK_CCH 0x0008
519 #define PCI_REG_B2BBASE0_VID 0x000C
520 #define PCI_REG_B2BBASE1_SID 0x0010
521 #define PCI_REG_MWMASK_DEV 0x0014
522 #define PCI_REG_MWBASE_REV_CCL 0x0018
523 #define PCI_REG_ERR_ADDR 0x001C
524 #define PCI_REG_SPEC_INTACK 0x0020
525 #define PCI_REG_ID 0x0100
526 #define PCI_REG_STATCMD 0x0104
527 #define PCI_REG_CLASSREV 0x0108
528 #define PCI_REG_PARAM 0x010C
529 #define PCI_REG_MBAR 0x0110
530 #define PCI_REG_TIMEOUT 0x0140
534 #define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14)
535 #define PCI_CMEM_CMMASK(x) ((x) & 0x3fff)
552 #define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */
561 #define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */
562 #define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16)
563 #define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */
564 #define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16)
565 #define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff)
566 #define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16)
567 #define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff)
568 #define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
569 #define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff)
570 #define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)
571 #define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8)
572 #define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff)
573 #define PCI_ID_DID(x) (((x) & 0xffff) << 16)
574 #define PCI_ID_VID(x) ((x) & 0xffff)
575 #define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16)
576 #define PCI_STATCMD_CMD(x) ((x) & 0xffff)
577 #define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8)
578 #define PCI_CLASSREV_REV(x) ((x) & 0xff)
579 #define PCI_PARAM_BIST(x) (((x) & 0xff) << 24)
580 #define PCI_PARAM_HT(x) (((x) & 0xff) << 16)
581 #define PCI_PARAM_LT(x) (((x) & 0xff) << 8)
582 #define PCI_PARAM_CLS(x) ((x) & 0xff)
583 #define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */
584 #define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */
639 case 0x00030100: /* Au1000 DA */ in au1xxx_cpu_has_pll_wo()
640 case 0x00030201: /* Au1000 HA */ in au1xxx_cpu_has_pll_wo()
641 case 0x00030202: /* Au1000 HB */ in au1xxx_cpu_has_pll_wo()
644 return 0; in au1xxx_cpu_has_pll_wo()
651 * c0_config.od (bit 19) was write only (and read as 0) on the in au1xxx_cpu_needs_config_od()
656 case 0x00030100: /* Au1000 DA */ in au1xxx_cpu_needs_config_od()
657 case 0x00030201: /* Au1000 HA */ in au1xxx_cpu_needs_config_od()
658 case 0x00030202: /* Au1000 HB */ in au1xxx_cpu_needs_config_od()
659 case 0x01030200: /* Au1500 AB */ in au1xxx_cpu_needs_config_od()
665 case 0x02030200: /* Au1100 AB */ in au1xxx_cpu_needs_config_od()
666 case 0x02030201: /* Au1100 BA */ in au1xxx_cpu_needs_config_od()
667 case 0x02030202: /* Au1100 BC */ in au1xxx_cpu_needs_config_od()
668 case 0x04030201: /* Au1200 AC */ in au1xxx_cpu_needs_config_od()
671 return 0; in au1xxx_cpu_needs_config_od()
675 #define ALCHEMY_CPU_AU1000 0
685 case 0x00030000: in alchemy_get_cputype()
688 case 0x01030000: in alchemy_get_cputype()
691 case 0x02030000: in alchemy_get_cputype()
694 case 0x03030000: in alchemy_get_cputype()
697 case 0x04030000: in alchemy_get_cputype()
698 case 0x05030000: in alchemy_get_cputype()
701 case 0x800c0000: in alchemy_get_cputype()
723 return 0; in alchemy_get_uarts()
732 if ((__raw_readl(addr + 0x100) & 3) != 3) { in alchemy_uart_enable()
733 __raw_writel(0, addr + 0x100); in alchemy_uart_enable()
735 __raw_writel(1, addr + 0x100); in alchemy_uart_enable()
738 __raw_writel(3, addr + 0x100); in alchemy_uart_enable()
746 __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */ in alchemy_uart_disable()
756 timeout = 0xffffff; in alchemy_uart_putchar()
758 if (__raw_readl(base + 0x1c) & 0x20) in alchemy_uart_putchar()
765 __raw_writel(c, base + 0x04); /* tx */ in alchemy_uart_putchar()
780 return 0; in alchemy_get_macs()
813 #define AU1000_IRDA_PHY_MODE_OFF 0
828 /* wake-from-str pins 0-3 */
829 AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
886 AU1300_VSS_MPE = 0,