Lines Matching +full:multi +full:- +full:processors
1 /* SPDX-License-Identifier: GPL-2.0 */
18 +----------------+----------------+----------------+----------------+
20 +----------------+----------------+----------------+----------------+
23 I don't have docs for all the previous processors, but my impression is
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
92 #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
95 #define PRID_IMP_LOONGSON_64R 0x6100 /* Reduced Loongson-2 */
96 #define PRID_IMP_LOONGSON_64C 0x6300 /* Classic Loongson-2 and Loongson-3 */
97 #define PRID_IMP_LOONGSON_64G 0xc000 /* Generic Loongson-2 and Loongson-3 */
232 * Definitions for 7:0 on legacy processors
267 * Older processors used to encode processor version and revision in two
268 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
269 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
280 * +---------------------------------+----------------+----------------+
282 * +---------------------------------+----------------+----------------+
296 * R2000 class processors
302 * R4000 class processors
311 * MIPS32 class processors
320 * MIPS64 class processors
361 #define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
362 #define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
375 #define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17) /* P-cache subset enforced */
387 #define MIPS_CPU_RIXIEX BIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit …
394 #define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */
397 #define MIPS_CPU_VP BIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
418 #define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */
419 #define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */
420 #define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instructi…
429 #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */