Lines Matching +full:dw +full:- +full:apb +full:- +full:ssi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
32 cpu_clk: cpu-clock {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <500000000>;
38 ahb_clk: ahb-clk {
39 compatible = "fixed-factor-clock";
40 #clock-cells = <0>;
42 clock-div = <2>;
43 clock-mult = <1>;
47 compatible = "simple-bus";
48 #address-cells = <1>;
49 #size-cells = <1>;
52 interrupt-parent = <&intc>;
55 compatible = "mscc,ocelot-cpu-syscon", "syscon";
59 intc: interrupt-controller@70 {
60 compatible = "mscc,ocelot-icpu-intr";
62 #interrupt-cells = <1>;
63 interrupt-controller;
64 interrupt-parent = <&cpuintc>;
69 pinctrl-0 = <&uart_pins>;
70 pinctrl-names = "default";
75 reg-io-width = <4>;
76 reg-shift = <2>;
82 compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
83 pinctrl-0 = <&i2c_pins>;
84 pinctrl-names = "default";
86 #address-cells = <1>;
87 #size-cells = <0>;
95 pinctrl-0 = <&uart2_pins>;
96 pinctrl-names = "default";
101 reg-io-width = <4>;
102 reg-shift = <2>;
108 compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
109 #address-cells = <1>;
110 #size-cells = <0>;
119 compatible = "mscc,vsc7514-switch";
141 reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
146 interrupt-names = "ptp_rdy", "xtr", "inj", "fdma";
148 ethernet-ports {
149 #address-cells = <1>;
150 #size-cells = <0>;
200 compatible = "mscc,ocelot-chip-reset";
205 compatible = "mscc,ocelot-pinctrl";
207 gpio-controller;
208 #gpio-cells = <2>;
209 gpio-ranges = <&gpio 0 0 22>;
210 interrupt-controller;
212 #interrupt-cells = <2>;
214 i2c_pins: i2c-pins {
219 uart_pins: uart-pins {
224 uart2_pins: uart2-pins {
229 miim1_pins: miim1-pins {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "mscc,ocelot-miim";
244 phy0: ethernet-phy@0 {
247 phy1: ethernet-phy@1 {
250 phy2: ethernet-phy@2 {
253 phy3: ethernet-phy@3 {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 compatible = "mscc,ocelot-miim";
264 pinctrl-names = "default";
265 pinctrl-0 = <&miim1_pins>;
270 compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
274 compatible = "mscc,vsc7514-serdes";
275 #phy-cells = <2>;