Lines Matching +full:i2c +full:- +full:arb
1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <81000000>;
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <27000000>;
47 #address-cells = <1>;
48 #size-cells = <1>;
50 compatible = "simple-bus";
53 periph_intc: interrupt-controller@411400 {
54 compatible = "brcm,bcm7038-l1-intc";
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
65 compatible = "brcm,l2-intc";
67 interrupt-controller;
68 #interrupt-cells = <1>;
69 interrupt-parent = <&periph_intc>;
73 gisb-arb@400000 {
74 compatible = "brcm,bcm7400-gisb-arb";
76 native-endian;
77 interrupt-parent = <&sun_l2_intc>;
79 brcm,gisb-arb-master-mask = <0x2f3>;
80 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
85 upg_irq0_intc: interrupt-controller@406600 {
86 compatible = "brcm,bcm7120-l2-intc";
89 brcm,int-map-mask = <0x44>, <0x7000000>;
90 brcm,int-fwd-mask = <0x70000>;
92 interrupt-controller;
93 #interrupt-cells = <1>;
95 interrupt-parent = <&periph_intc>;
97 interrupt-names = "upg_main", "upg_bsc";
100 upg_aon_irq0_intc: interrupt-controller@408b80 {
101 compatible = "brcm,bcm7120-l2-intc";
104 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
105 brcm,int-fwd-mask = <0>;
106 brcm,irq-can-wake;
108 interrupt-controller;
109 #interrupt-cells = <1>;
111 interrupt-parent = <&periph_intc>;
113 interrupt-names = "upg_main_aon", "upg_bsc_aon",
118 compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
120 native-endian;
124 compatible = "brcm,brcmstb-reboot";
131 reg-io-width = <0x4>;
132 reg-shift = <0x2>;
133 native-endian;
134 interrupt-parent = <&periph_intc>;
143 reg-io-width = <0x4>;
144 reg-shift = <0x2>;
145 native-endian;
146 interrupt-parent = <&periph_intc>;
155 reg-io-width = <0x4>;
156 reg-shift = <0x2>;
157 native-endian;
158 interrupt-parent = <&periph_intc>;
164 bsca: i2c@406200 {
165 clock-frequency = <390000>;
166 compatible = "brcm,brcmstb-i2c";
167 interrupt-parent = <&upg_irq0_intc>;
170 interrupt-names = "upg_bsca";
174 bscb: i2c@406280 {
175 clock-frequency = <390000>;
176 compatible = "brcm,brcmstb-i2c";
177 interrupt-parent = <&upg_irq0_intc>;
180 interrupt-names = "upg_bscb";
184 bscc: i2c@406300 {
185 clock-frequency = <390000>;
186 compatible = "brcm,brcmstb-i2c";
187 interrupt-parent = <&upg_irq0_intc>;
190 interrupt-names = "upg_bscc";
194 bscd: i2c@408980 {
195 clock-frequency = <390000>;
196 compatible = "brcm,brcmstb-i2c";
197 interrupt-parent = <&upg_aon_irq0_intc>;
200 interrupt-names = "upg_bscd";
205 compatible = "brcm,bcm7038-pwm";
207 #pwm-cells = <2>;
213 compatible = "brcm,bcm7038-pwm";
215 #pwm-cells = <2>;
222 compatible = "brcm,bcm7038-wdt";
227 aon_pm_l2_intc: interrupt-controller@408240 {
228 compatible = "brcm,l2-intc";
230 interrupt-controller;
231 #interrupt-cells = <1>;
232 interrupt-parent = <&periph_intc>;
234 brcm,irq-can-wake;
238 compatible = "brcm,brcmstb-gpio";
240 #gpio-cells = <2>;
241 #interrupt-cells = <2>;
242 gpio-controller;
243 interrupt-controller;
244 interrupt-parent = <&upg_irq0_intc>;
246 brcm,gpio-bank-widths = <32 32 32 29 4>;
250 compatible = "brcm,brcmstb-gpio";
252 #gpio-cells = <2>;
253 #interrupt-cells = <2>;
254 gpio-controller;
255 interrupt-controller;
256 interrupt-parent = <&upg_aon_irq0_intc>;
258 interrupts-extended = <&upg_aon_irq0_intc 6>,
260 wakeup-source;
261 brcm,gpio-bank-widths = <21 32 2>;
265 phy-mode = "internal";
266 phy-handle = <&phy1>;
267 mac-address = [ 00 10 18 36 23 1a ];
268 compatible = "brcm,genet-v2";
269 #address-cells = <0x1>;
270 #size-cells = <0x1>;
273 interrupt-parent = <&periph_intc>;
277 compatible = "brcm,genet-mdio-v2";
278 #address-cells = <0x1>;
279 #size-cells = <0x0>;
282 phy1: ethernet-phy@1 {
283 max-speed = <100>;
285 compatible = "brcm,40nm-ephy",
286 "ethernet-phy-ieee802.3-c22";
292 compatible = "brcm,bcm7358-ehci", "generic-ehci";
294 native-endian;
295 interrupt-parent = <&periph_intc>;
301 compatible = "brcm,bcm7358-ohci", "generic-ohci";
303 native-endian;
304 no-big-frame-no;
305 interrupt-parent = <&periph_intc>;
310 hif_l2_intc: interrupt-controller@411000 {
311 compatible = "brcm,l2-intc";
313 interrupt-controller;
314 #interrupt-cells = <1>;
315 interrupt-parent = <&periph_intc>;
320 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 reg-names = "nand";
325 interrupt-parent = <&hif_l2_intc>;
330 spi_l2_intc: interrupt-controller@411d00 {
331 compatible = "brcm,l2-intc";
333 interrupt-controller;
334 #interrupt-cells = <1>;
335 interrupt-parent = <&periph_intc>;
340 #address-cells = <0x1>;
341 #size-cells = <0x0>;
342 compatible = "brcm,spi-bcm-qspi",
343 "brcm,spi-brcmstb-qspi";
346 reg-names = "cs_reg", "hif_mspi", "bspi";
348 interrupt-parent = <&spi_l2_intc>;
349 interrupt-names = "spi_lr_fullness_reached",
360 #address-cells = <1>;
361 #size-cells = <0>;
362 compatible = "brcm,spi-bcm-qspi",
363 "brcm,spi-brcmstb-mspi";
366 reg-names = "mspi";
368 interrupt-parent = <&upg_aon_irq0_intc>;
369 interrupt-names = "mspi_done";
374 compatible = "brcm,brcmstb-waketimer";
377 interrupt-parent = <&aon_pm_l2_intc>;
378 interrupt-names = "timer";