Lines Matching +full:i2c +full:- +full:arb
1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <81000000>;
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <27000000>;
53 #address-cells = <1>;
54 #size-cells = <1>;
56 compatible = "simple-bus";
59 periph_intc: interrupt-controller@411400 {
60 compatible = "brcm,bcm7038-l1-intc";
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
71 compatible = "brcm,l2-intc";
73 interrupt-controller;
74 #interrupt-cells = <1>;
75 interrupt-parent = <&periph_intc>;
79 gisb-arb@400000 {
80 compatible = "brcm,bcm7400-gisb-arb";
82 native-endian;
83 interrupt-parent = <&sun_l2_intc>;
85 brcm,gisb-arb-master-mask = <0x673>;
86 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
91 upg_irq0_intc: interrupt-controller@406780 {
92 compatible = "brcm,bcm7120-l2-intc";
95 brcm,int-map-mask = <0x44>, <0xf000000>;
96 brcm,int-fwd-mask = <0x70000>;
98 interrupt-controller;
99 #interrupt-cells = <1>;
101 interrupt-parent = <&periph_intc>;
103 interrupt-names = "upg_main", "upg_bsc";
106 upg_aon_irq0_intc: interrupt-controller@408b80 {
107 compatible = "brcm,bcm7120-l2-intc";
110 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
111 brcm,int-fwd-mask = <0>;
112 brcm,irq-can-wake;
114 interrupt-controller;
115 #interrupt-cells = <1>;
117 interrupt-parent = <&periph_intc>;
119 interrupt-names = "upg_main_aon", "upg_bsc_aon",
124 compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
126 native-endian;
130 compatible = "brcm,brcmstb-reboot";
137 reg-io-width = <0x4>;
138 reg-shift = <0x2>;
139 native-endian;
140 interrupt-parent = <&periph_intc>;
149 reg-io-width = <0x4>;
150 reg-shift = <0x2>;
151 native-endian;
152 interrupt-parent = <&periph_intc>;
161 reg-io-width = <0x4>;
162 reg-shift = <0x2>;
163 native-endian;
164 interrupt-parent = <&periph_intc>;
170 bsca: i2c@406200 {
171 clock-frequency = <390000>;
172 compatible = "brcm,brcmstb-i2c";
173 interrupt-parent = <&upg_irq0_intc>;
176 interrupt-names = "upg_bsca";
180 bscb: i2c@406280 {
181 clock-frequency = <390000>;
182 compatible = "brcm,brcmstb-i2c";
183 interrupt-parent = <&upg_irq0_intc>;
186 interrupt-names = "upg_bscb";
190 bscc: i2c@406300 {
191 clock-frequency = <390000>;
192 compatible = "brcm,brcmstb-i2c";
193 interrupt-parent = <&upg_irq0_intc>;
196 interrupt-names = "upg_bscc";
200 bscd: i2c@406380 {
201 clock-frequency = <390000>;
202 compatible = "brcm,brcmstb-i2c";
203 interrupt-parent = <&upg_irq0_intc>;
206 interrupt-names = "upg_bscd";
210 bsce: i2c@408980 {
211 clock-frequency = <390000>;
212 compatible = "brcm,brcmstb-i2c";
213 interrupt-parent = <&upg_aon_irq0_intc>;
216 interrupt-names = "upg_bsce";
221 compatible = "brcm,bcm7038-pwm";
223 #pwm-cells = <2>;
229 compatible = "brcm,bcm7038-pwm";
231 #pwm-cells = <2>;
238 compatible = "brcm,bcm7038-wdt";
243 aon_pm_l2_intc: interrupt-controller@408440 {
244 compatible = "brcm,l2-intc";
246 interrupt-controller;
247 #interrupt-cells = <1>;
248 interrupt-parent = <&periph_intc>;
250 brcm,irq-can-wake;
254 compatible = "brcm,brcmstb-aon-ctrl";
256 reg-names = "aon-ctrl", "aon-sram";
260 compatible = "brcm,brcmstb-timers";
265 compatible = "brcm,brcmstb-gpio";
267 #gpio-cells = <2>;
268 #interrupt-cells = <2>;
269 gpio-controller;
270 interrupt-controller;
271 interrupt-parent = <&upg_irq0_intc>;
273 brcm,gpio-bank-widths = <32 32 16>;
277 compatible = "brcm,brcmstb-gpio";
279 #gpio-cells = <2>;
280 #interrupt-cells = <2>;
281 gpio-controller;
282 interrupt-controller;
283 interrupt-parent = <&upg_aon_irq0_intc>;
285 interrupts-extended = <&upg_aon_irq0_intc 6>,
287 wakeup-source;
288 brcm,gpio-bank-widths = <27 32 2>;
292 phy-mode = "internal";
293 phy-handle = <&phy1>;
294 mac-address = [ 00 10 18 36 23 1a ];
295 compatible = "brcm,genet-v2";
296 #address-cells = <0x1>;
297 #size-cells = <0x1>;
300 interrupt-parent = <&periph_intc>;
304 compatible = "brcm,genet-mdio-v2";
305 #address-cells = <0x1>;
306 #size-cells = <0x0>;
309 phy1: ethernet-phy@1 {
310 max-speed = <100>;
312 compatible = "brcm,40nm-ephy",
313 "ethernet-phy-ieee802.3-c22";
319 compatible = "brcm,bcm7346-ehci", "generic-ehci";
321 native-endian;
322 interrupt-parent = <&periph_intc>;
328 compatible = "brcm,bcm7346-ohci", "generic-ohci";
330 native-endian;
331 no-big-frame-no;
332 interrupt-parent = <&periph_intc>;
338 compatible = "brcm,bcm7346-ehci", "generic-ehci";
340 native-endian;
341 interrupt-parent = <&periph_intc>;
347 compatible = "brcm,bcm7346-ohci", "generic-ohci";
349 native-endian;
350 no-big-frame-no;
351 interrupt-parent = <&periph_intc>;
357 compatible = "brcm,bcm7346-ehci", "generic-ehci";
359 native-endian;
360 interrupt-parent = <&periph_intc>;
366 compatible = "brcm,bcm7346-ohci", "generic-ohci";
368 native-endian;
369 no-big-frame-no;
370 interrupt-parent = <&periph_intc>;
376 compatible = "brcm,bcm7346-ehci", "generic-ehci";
378 native-endian;
379 interrupt-parent = <&periph_intc>;
385 compatible = "brcm,bcm7346-ohci", "generic-ohci";
387 native-endian;
388 no-big-frame-no;
389 interrupt-parent = <&periph_intc>;
394 hif_l2_intc: interrupt-controller@411000 {
395 compatible = "brcm,l2-intc";
397 interrupt-controller;
398 #interrupt-cells = <1>;
399 interrupt-parent = <&periph_intc>;
404 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
405 #address-cells = <1>;
406 #size-cells = <0>;
407 reg-names = "nand";
409 interrupt-parent = <&hif_l2_intc>;
415 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
416 reg-names = "ahci", "top-ctrl";
418 interrupt-parent = <&periph_intc>;
420 #address-cells = <1>;
421 #size-cells = <0>;
424 sata0: sata-port@0 {
429 sata1: sata-port@1 {
435 sata_phy: sata-phy@180100 {
436 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
438 reg-names = "phy";
439 #address-cells = <1>;
440 #size-cells = <0>;
443 sata_phy0: sata-phy@0 {
445 #phy-cells = <0>;
448 sata_phy1: sata-phy@1 {
450 #phy-cells = <0>;
455 compatible = "brcm,bcm7425-sdhci";
457 interrupt-parent = <&periph_intc>;
462 spi_l2_intc: interrupt-controller@411d00 {
463 compatible = "brcm,l2-intc";
465 interrupt-controller;
466 #interrupt-cells = <1>;
467 interrupt-parent = <&periph_intc>;
472 #address-cells = <0x1>;
473 #size-cells = <0x0>;
474 compatible = "brcm,spi-bcm-qspi",
475 "brcm,spi-brcmstb-qspi";
478 reg-names = "cs_reg", "hif_mspi", "bspi";
480 interrupt-parent = <&spi_l2_intc>;
481 interrupt-names = "spi_lr_fullness_reached",
492 #address-cells = <1>;
493 #size-cells = <0>;
494 compatible = "brcm,spi-bcm-qspi",
495 "brcm,spi-brcmstb-mspi";
498 reg-names = "mspi";
500 interrupt-parent = <&upg_aon_irq0_intc>;
501 interrupt-names = "mspi_done";
506 compatible = "brcm,brcmstb-waketimer";
509 interrupt-parent = <&aon_pm_l2_intc>;
510 interrupt-names = "timer";
517 compatible = "simple-bus";
519 #address-cells = <1>;
520 #size-cells = <1>;
522 memory-controller@0 {
523 compatible = "brcm,brcmstb-memc", "simple-bus";
525 #address-cells = <1>;
526 #size-cells = <1>;
528 memc-arb@1000 {
529 compatible = "brcm,brcmstb-memc-arb";
533 memc-ddr@2000 {
534 compatible = "brcm,brcmstb-memc-ddr";
538 ddr-phy@6000 {
539 compatible = "brcm,brcmstb-ddr-phy";
544 compatible = "brcm,brcmstb-ddr-shimphy";