Lines Matching +full:i2c +full:- +full:arb
1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <202500000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <81000000>;
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <27000000>;
53 #address-cells = <1>;
54 #size-cells = <1>;
56 compatible = "simple-bus";
59 periph_intc: interrupt-controller@441400 {
60 compatible = "brcm,bcm7038-l1-intc";
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
71 compatible = "brcm,l2-intc";
73 interrupt-controller;
74 #interrupt-cells = <1>;
75 interrupt-parent = <&periph_intc>;
79 gisb-arb@400000 {
80 compatible = "brcm,bcm7400-gisb-arb";
82 native-endian;
83 interrupt-parent = <&sun_l2_intc>;
85 brcm,gisb-arb-master-mask = <0x2f7>;
86 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
91 upg_irq0_intc: interrupt-controller@406780 {
92 compatible = "brcm,bcm7120-l2-intc";
95 brcm,int-map-mask = <0x44>, <0xf000000>, <0x100000>;
96 brcm,int-fwd-mask = <0x70000>;
98 interrupt-controller;
99 #interrupt-cells = <1>;
101 interrupt-parent = <&periph_intc>;
103 interrupt-names = "upg_main", "upg_bsc", "upg_spi";
107 compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
109 native-endian;
113 compatible = "brcm,bcm7038-reboot";
120 reg-io-width = <0x4>;
121 reg-shift = <0x2>;
122 native-endian;
123 interrupt-parent = <&periph_intc>;
132 reg-io-width = <0x4>;
133 reg-shift = <0x2>;
134 native-endian;
135 interrupt-parent = <&periph_intc>;
144 reg-io-width = <0x4>;
145 reg-shift = <0x2>;
146 native-endian;
147 interrupt-parent = <&periph_intc>;
153 bsca: i2c@406200 {
154 clock-frequency = <390000>;
155 compatible = "brcm,brcmstb-i2c";
156 interrupt-parent = <&upg_irq0_intc>;
159 interrupt-names = "upg_bsca";
163 bscb: i2c@406280 {
164 clock-frequency = <390000>;
165 compatible = "brcm,brcmstb-i2c";
166 interrupt-parent = <&upg_irq0_intc>;
169 interrupt-names = "upg_bscb";
173 bscc: i2c@406300 {
174 clock-frequency = <390000>;
175 compatible = "brcm,brcmstb-i2c";
176 interrupt-parent = <&upg_irq0_intc>;
179 interrupt-names = "upg_bscc";
183 bscd: i2c@406380 {
184 clock-frequency = <390000>;
185 compatible = "brcm,brcmstb-i2c";
186 interrupt-parent = <&upg_irq0_intc>;
189 interrupt-names = "upg_bscd";
194 compatible = "brcm,bcm7038-pwm";
196 #pwm-cells = <2>;
203 compatible = "brcm,bcm7038-wdt";
209 compatible = "brcm,brcmstb-gpio";
211 #gpio-cells = <2>;
212 #interrupt-cells = <2>;
213 gpio-controller;
214 interrupt-controller;
215 interrupt-parent = <&upg_irq0_intc>;
217 brcm,gpio-bank-widths = <32 32 32 18>;
221 compatible = "brcm,bcm7125-ehci", "generic-ehci";
223 native-endian;
224 interrupt-parent = <&periph_intc>;
230 compatible = "brcm,bcm7125-ohci", "generic-ohci";
232 native-endian;
233 interrupt-parent = <&periph_intc>;
238 spi_l2_intc: interrupt-controller@411d00 {
239 compatible = "brcm,l2-intc";
241 interrupt-controller;
242 #interrupt-cells = <1>;
243 interrupt-parent = <&periph_intc>;
248 #address-cells = <0x1>;
249 #size-cells = <0x0>;
250 compatible = "brcm,spi-bcm-qspi",
251 "brcm,spi-brcmstb-qspi";
254 reg-names = "cs_reg", "hif_mspi", "bspi";
256 interrupt-parent = <&spi_l2_intc>;
257 interrupt-names = "spi_lr_fullness_reached",
268 #address-cells = <1>;
269 #size-cells = <0>;
270 compatible = "brcm,spi-bcm-qspi",
271 "brcm,spi-brcmstb-mspi";
274 reg-names = "mspi";
276 interrupt-parent = <&upg_irq0_intc>;
277 interrupt-names = "mspi_done";