35 #define BCSR_INT_IDE		0x0001
36 #define BCSR_INT_ETH		0x0002
37 #define BCSR_INT_PC0		0x0004
38 #define BCSR_INT_PC0STSCHG	0x0008
39 #define BCSR_INT_PC1		0x0010
40 #define BCSR_INT_PC1STSCHG	0x0020
41 #define BCSR_INT_DC		0x0040
42 #define BCSR_INT_FLASHBUSY	0x0080
43 #define BCSR_INT_PC0INSERT	0x0100
44 #define BCSR_INT_PC0EJECT	0x0200
45 #define BCSR_INT_PC1INSERT	0x0400
46 #define BCSR_INT_PC1EJECT	0x0800
47 #define BCSR_INT_SD0INSERT	0x1000
48 #define BCSR_INT_SD0EJECT	0x2000
49 #define BCSR_INT_SD1INSERT	0x4000
50 #define BCSR_INT_SD1EJECT	0x8000
52 #define DB1200_IDE_PHYS_ADDR	0x18800000
55 #define DB1200_ETH_PHYS_ADDR	0x19000300
56 #define DB1200_NAND_PHYS_ADDR	0x20000000
58 #define PB1200_IDE_PHYS_ADDR	0x0C800000
59 #define PB1200_ETH_PHYS_ADDR	0x0D000300
60 #define PB1200_NAND_PHYS_ADDR	0x1C000000
63 #define DB1200_IDE_INT		(DB1200_INT_BEGIN + 0)
95 			return 0;  in db1200_detect_board()
109 			return 0;  in db1200_detect_board()
135 		(whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);  in db1200_board_setup()
137 	return 0;  in db1200_board_setup()
147 		.offset = 0,
164 		.bus_num	= 0,
165 		.chip_select	= 0,
166 		.mode		= 0,
172 		.bus_num	= 0,
174 		.mode		= 0,
180 	{ I2C_BOARD_INFO("24c04", 0x52),  }, /* AT24C04-10 I2C eeprom */
181 	{ I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
182 	{ I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */
192 	ioaddr &= 0xffffff00;  in au1200_nand_cmd_ctrl()
216 		.name	= "NAND FS 0",
217 		.offset = 0,
230 		.chip_offset	= 0,
242 	[0] = {
244 		.end	= DB1200_NAND_PHYS_ADDR + 0xff,
268 	[0] = {
270 		.end	= DB1200_ETH_PHYS_ADDR + 0xf,
298 	[0] = {
317 	.id		= 0,
360 				db1200_mmc_cdfn, 0, "sd_insert", mmc_host);  in db1200_mmc_cd_setup()
365 				db1200_mmc_cdfn, 0, "sd_eject", mmc_host);  in db1200_mmc_cd_setup()
380 	ret = 0;  in db1200_mmc_cd_setup()
388 		bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);  in db1200_mmc_set_power()
391 		bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);  in db1200_mmc_set_power()
396 	return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;  in db1200_mmc_card_readonly()
401 	return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;  in db1200_mmc_card_inserted()
408 		bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);  in db1200_mmcled_set()
410 		bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);  in db1200_mmcled_set()
444 				pb1200_mmc1_cdfn, 0, "sd1_insert", mmc_host);  in pb1200_mmc1_cd_setup()
449 				pb1200_mmc1_cdfn, 0, "sd1_eject", mmc_host);  in pb1200_mmc1_cd_setup()
464 	ret = 0;  in pb1200_mmc1_cd_setup()
473 			bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);  in pb1200_mmc1led_set()
475 			bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);  in pb1200_mmc1led_set()
485 		bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);  in pb1200_mmc1_set_power()
488 		bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);  in pb1200_mmc1_set_power()
493 	return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;  in pb1200_mmc1_card_readonly()
498 	return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;  in pb1200_mmc1_card_inserted()
503 	[0] = {
520 	[0] = {
522 		.end	= AU1100_SD0_PHYS_ADDR + 0xfff,
544 	.id		= 0,
548 		.platform_data		= &db1200_mmc_platdata[0],
555 	[0] = {
557 		.end	= AU1100_SD1_PHYS_ADDR + 0xfff,
594 	return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;  in db1200fb_panel_index()
600 	bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |  in db1200fb_panel_init()
602 	return 0;  in db1200fb_panel_init()
609 			     BCSR_BOARD_LCDBL, 0);  in db1200fb_panel_shutdown()
610 	return 0;  in db1200fb_panel_shutdown()
620 	[0] = {
622 		.end	= AU1200_LCD_PHYS_ADDR + 0x800 - 1,
634 	.id		= 0,
647 	[0] = {
649 		.end	= AU1550_PSC0_PHYS_ADDR + 0xfff,
671 	.id		= 0,	/* bus number */
679 		bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);  in db1200_spi_cs_en()
681 		bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);  in db1200_spi_cs_en()
697 	.id		= 0,	/* bus number */
703 	[0] = {
705 		.end	= AU1550_PSC1_PHYS_ADDR + 0xfff,
790 	db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;  in pb1200_res_fixup()
791 	db1200_nand_res[0].end	 = PB1200_NAND_PHYS_ADDR + 0xff;  in pb1200_res_fixup()
792 	db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;  in pb1200_res_fixup()
793 	db1200_ide_res[0].end	= PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;  in pb1200_res_fixup()
794 	db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;  in pb1200_res_fixup()
795 	db1200_eth_res[0].end	= PB1200_ETH_PHYS_ADDR + 0xff;  in pb1200_res_fixup()
796 	return 0;  in pb1200_res_fixup()
847 	i2c_register_board_info(0, db1200_i2c_devs,  in db1200_dev_setup()
873 		db1200_devs[0] = &db1200_i2c_dev;  in db1200_dev_setup()
874 		bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);  in db1200_dev_setup()
881 		db1200_devs[0] = &db1200_spi_dev;  in db1200_dev_setup()
882 		bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);  in db1200_dev_setup()
891 	/* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!  in db1200_dev_setup()
892 	 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S  in db1200_dev_setup()
896 		bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);  in db1200_dev_setup()
901 		bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);  in db1200_dev_setup()
914 		AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,  in db1200_dev_setup()
916 		AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,  in db1200_dev_setup()
918 		AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,  in db1200_dev_setup()
920 		/*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);  in db1200_dev_setup()
923 		AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,  in db1200_dev_setup()
924 		AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,  in db1200_dev_setup()
925 		AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,  in db1200_dev_setup()
926 		AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,  in db1200_dev_setup()
927 		AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,  in db1200_dev_setup()
928 		AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,  in db1200_dev_setup()
930 		/*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);  in db1200_dev_setup()
942 	return 0;  in db1200_dev_setup()