Lines Matching full:ohci
5 * Au1000+: The OHCI block control register is at the far end of the OHCI memory
6 * area. Au1550 has OHCI on different base address. No need to handle
28 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
29 #define USBHEN_CE (1 << 3) /* OHCI block clock enable */
30 #define USBHEN_E (1 << 2) /* OHCI block enable */
31 #define USBHEN_C (1 << 1) /* OHCI block coherency bit */
32 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
42 #define USBCFG_OCE (1 << 16) /* OHCI clock enable */
50 #define USBCFG_OBE (1 << 1) /* OHCI busmaster enable */
51 #define USBCFG_OME (1 << 0) /* OHCI mem enable */
128 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ in __au1300_ohci_control()
131 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ in __au1300_ohci_control()
144 /* reset the OHCI start clock bit */ in __au1300_ohci_control()