15  *     or [1 .. 256 in steps of 1] (Au1300),
20  *   * divide this input by 1, 2, or 4 (and 3 on Au1300).
111 /* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
163 	id.num_parents = 1;  in alchemy_clk_setup_cpu()
245 	struct clk *c;  in alchemy_clk_setup_aux()  local
254 	id.num_parents = 1;  in alchemy_clk_setup_aux()
262 	c = clk_register(NULL, &a->hw);  in alchemy_clk_setup_aux()
263 	if (!IS_ERR(c))  in alchemy_clk_setup_aux()
264 		clk_register_clkdev(c, name, NULL);  in alchemy_clk_setup_aux()
268 	return c;  in alchemy_clk_setup_aux()
276 	struct clk *c;  in alchemy_clk_setup_sysbus()  local
278 	c = clk_register_fixed_factor(NULL, ALCHEMY_SYSBUS_CLK,  in alchemy_clk_setup_sysbus()
279 				      pn, 0, 1, v);  in alchemy_clk_setup_sysbus()
280 	if (!IS_ERR(c))  in alchemy_clk_setup_sysbus()
281 		clk_register_clkdev(c, ALCHEMY_SYSBUS_CLK, NULL);  in alchemy_clk_setup_sysbus()
282 	return c;  in alchemy_clk_setup_sysbus()
290 	struct clk *c;  in alchemy_clk_setup_periph()  local
292 	c = clk_register_fixed_factor(NULL, ALCHEMY_PERIPH_CLK,  in alchemy_clk_setup_periph()
293 				      pn, 0, 1, 2);  in alchemy_clk_setup_periph()
294 	if (!IS_ERR(c))  in alchemy_clk_setup_periph()
295 		clk_register_clkdev(c, ALCHEMY_PERIPH_CLK, NULL);  in alchemy_clk_setup_periph()
296 	return c;  in alchemy_clk_setup_periph()
305 	struct clk *c;  in alchemy_clk_setup_mem()  local
312 		div = (v & (1 << 15)) ? 1 : 2;  in alchemy_clk_setup_mem()
316 		div = (v & (1 << 31)) ? 1 : 2;  in alchemy_clk_setup_mem()
326 	c = clk_register_fixed_factor(NULL, ALCHEMY_MEM_CLK, pn,  in alchemy_clk_setup_mem()
327 				      0, 1, div);  in alchemy_clk_setup_mem()
328 	if (!IS_ERR(c))  in alchemy_clk_setup_mem()
329 		clk_register_clkdev(c, ALCHEMY_MEM_CLK, NULL);  in alchemy_clk_setup_mem()
330 	return c;  in alchemy_clk_setup_mem()
340 	 * L/RCLK = periph_clk / (divisor + 1)  in alchemy_clk_setup_lrclk()
344 	struct clk *c;  in alchemy_clk_setup_lrclk()  local
350 		v = 4 + ((v >> 11) & 1);  in alchemy_clk_setup_lrclk()
353 		v = ((v >> 13) & 7) + 1;  in alchemy_clk_setup_lrclk()
355 	c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,  in alchemy_clk_setup_lrclk()
356 				      pn, 0, 1, v);  in alchemy_clk_setup_lrclk()
357 	if (!IS_ERR(c))  in alchemy_clk_setup_lrclk()
358 		clk_register_clkdev(c, ALCHEMY_LR_CLK, NULL);  in alchemy_clk_setup_lrclk()
359 	return c;  in alchemy_clk_setup_lrclk()
368 	unsigned long reg;	/* SYS_FREQCTRL0/1		  */
386 		if (div1 & 1)  in alchemy_calc_div()
390 	div2 = (div1 / scale) - 1;	/* value to write to register */  in alchemy_calc_div()
397 	div1 = ((div2 + 1) * scale);  in alchemy_calc_div()
458 		for (j = (maxdiv == 4) ? 1 : scale; j <= maxdiv; j += scale) {  in alchemy_clk_fgcs_detr()
493 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv1_en()  local
496 	spin_lock_irqsave(c->reglock, flags);  in alchemy_clk_fgv1_en()
497 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv1_en()
498 	v |= (1 << 1) << c->shift;  in alchemy_clk_fgv1_en()
499 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv1_en()
500 	spin_unlock_irqrestore(c->reglock, flags);  in alchemy_clk_fgv1_en()
507 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv1_isen()  local
508 	unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1);  in alchemy_clk_fgv1_isen()
510 	return v & 1;  in alchemy_clk_fgv1_isen()
515 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv1_dis()  local
518 	spin_lock_irqsave(c->reglock, flags);  in alchemy_clk_fgv1_dis()
519 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv1_dis()
520 	v &= ~((1 << 1) << c->shift);  in alchemy_clk_fgv1_dis()
521 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv1_dis()
522 	spin_unlock_irqrestore(c->reglock, flags);  in alchemy_clk_fgv1_dis()
527 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv1_setp()  local
530 	spin_lock_irqsave(c->reglock, flags);  in alchemy_clk_fgv1_setp()
531 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv1_setp()
533 		v |= (1 << c->shift);  in alchemy_clk_fgv1_setp()
535 		v &= ~(1 << c->shift);  in alchemy_clk_fgv1_setp()
536 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv1_setp()
537 	spin_unlock_irqrestore(c->reglock, flags);  in alchemy_clk_fgv1_setp()
544 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv1_getp()  local
546 	return (alchemy_rdsys(c->reg) >> c->shift) & 1;  in alchemy_clk_fgv1_getp()
552 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv1_setr()  local
554 	int sh = c->shift + 2;  in alchemy_clk_fgv1_setr()
559 	spin_lock_irqsave(c->reglock, flags);  in alchemy_clk_fgv1_setr()
560 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv1_setr()
563 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv1_setr()
564 	spin_unlock_irqrestore(c->reglock, flags);  in alchemy_clk_fgv1_setr()
572 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv1_recalc()  local
573 	unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2);  in alchemy_clk_fgv1_recalc()
575 	v = ((v & 0xff) + 1) * 2;  in alchemy_clk_fgv1_recalc()
597 static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk *c)  in __alchemy_clk_fgv2_en()  argument
599 	unsigned long v = alchemy_rdsys(c->reg);  in __alchemy_clk_fgv2_en()
601 	v &= ~(3 << c->shift);  in __alchemy_clk_fgv2_en()
602 	v |= (c->parent & 3) << c->shift;  in __alchemy_clk_fgv2_en()
603 	alchemy_wrsys(v, c->reg);  in __alchemy_clk_fgv2_en()
604 	c->isen = 1;  in __alchemy_clk_fgv2_en()
609 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv2_en()  local
613 	spin_lock_irqsave(c->reglock, flags);  in alchemy_clk_fgv2_en()
614 	__alchemy_clk_fgv2_en(c);  in alchemy_clk_fgv2_en()
615 	spin_unlock_irqrestore(c->reglock, flags);  in alchemy_clk_fgv2_en()
622 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv2_isen()  local
624 	return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0;  in alchemy_clk_fgv2_isen()
629 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv2_dis()  local
632 	spin_lock_irqsave(c->reglock, flags);  in alchemy_clk_fgv2_dis()
633 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv2_dis()
634 	v &= ~(3 << c->shift);	/* set input mux to "disabled" state */  in alchemy_clk_fgv2_dis()
635 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv2_dis()
636 	c->isen = 0;  in alchemy_clk_fgv2_dis()
637 	spin_unlock_irqrestore(c->reglock, flags);  in alchemy_clk_fgv2_dis()
642 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv2_setp()  local
645 	spin_lock_irqsave(c->reglock, flags);  in alchemy_clk_fgv2_setp()
646 	c->parent = index + 1;	/* value to write to register */  in alchemy_clk_fgv2_setp()
647 	if (c->isen)  in alchemy_clk_fgv2_setp()
648 		__alchemy_clk_fgv2_en(c);  in alchemy_clk_fgv2_setp()
649 	spin_unlock_irqrestore(c->reglock, flags);  in alchemy_clk_fgv2_setp()
656 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv2_getp()  local
659 	spin_lock_irqsave(c->reglock, flags);  in alchemy_clk_fgv2_getp()
660 	v = c->parent - 1;  in alchemy_clk_fgv2_getp()
661 	spin_unlock_irqrestore(c->reglock, flags);  in alchemy_clk_fgv2_getp()
667  * of 2); with the bit set, dividers are multiples of 1, halving their
673 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv2_setr()  local
674 	int sh = c->shift + 2;  in alchemy_clk_fgv2_setr()
680 	v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */  in alchemy_clk_fgv2_setr()
681 	ret = alchemy_calc_div(rate, parent_rate, v ? 1 : 2,  in alchemy_clk_fgv2_setr()
684 	spin_lock_irqsave(c->reglock, flags);  in alchemy_clk_fgv2_setr()
685 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv2_setr()
688 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv2_setr()
689 	spin_unlock_irqrestore(c->reglock, flags);  in alchemy_clk_fgv2_setr()
697 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv2_recalc()  local
698 	int sh = c->shift + 2;  in alchemy_clk_fgv2_recalc()
701 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv2_recalc()
702 	t = parent_rate / (((v >> sh) & 0xff) + 1);  in alchemy_clk_fgv2_recalc()
703 	if ((v & (1 << 30)) == 0)		/* test scale bit */  in alchemy_clk_fgv2_recalc()
712 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_fgv2_detr()  local
715 	if (alchemy_rdsys(c->reg) & (1 << 30)) {  in alchemy_clk_fgv2_detr()
716 		scale = 1;  in alchemy_clk_fgv2_detr()
752 	struct clk *c;  in alchemy_clk_init_fgens()  local
799 				a->parent = 1;  in alchemy_clk_init_fgens()
802 				a->isen = 1;  in alchemy_clk_init_fgens()
806 		c = clk_register(NULL, &a->hw);  in alchemy_clk_init_fgens()
807 		if (IS_ERR(c))  in alchemy_clk_init_fgens()
810 			clk_register_clkdev(c, id.name, NULL);  in alchemy_clk_init_fgens()
821 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_csrc_isen()  local
822 	unsigned long v = alchemy_rdsys(c->reg);  in alchemy_clk_csrc_isen()
824 	return (((v >> c->shift) >> 2) & 7) != 0;  in alchemy_clk_csrc_isen()
827 static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk *c)  in __alchemy_clk_csrc_en()  argument
829 	unsigned long v = alchemy_rdsys(c->reg);  in __alchemy_clk_csrc_en()
831 	v &= ~((7 << 2) << c->shift);  in __alchemy_clk_csrc_en()
832 	v |= ((c->parent & 7) << 2) << c->shift;  in __alchemy_clk_csrc_en()
833 	alchemy_wrsys(v, c->reg);  in __alchemy_clk_csrc_en()
834 	c->isen = 1;  in __alchemy_clk_csrc_en()
839 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_csrc_en()  local
843 	spin_lock_irqsave(c->reglock, flags);  in alchemy_clk_csrc_en()
844 	__alchemy_clk_csrc_en(c);  in alchemy_clk_csrc_en()
845 	spin_unlock_irqrestore(c->reglock, flags);  in alchemy_clk_csrc_en()
852 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_csrc_dis()  local
855 	spin_lock_irqsave(c->reglock, flags);  in alchemy_clk_csrc_dis()
856 	v = alchemy_rdsys(c->reg);  in alchemy_clk_csrc_dis()
857 	v &= ~((3 << 2) << c->shift);	/* mux to "disabled" state */  in alchemy_clk_csrc_dis()
858 	alchemy_wrsys(v, c->reg);  in alchemy_clk_csrc_dis()
859 	c->isen = 0;  in alchemy_clk_csrc_dis()
860 	spin_unlock_irqrestore(c->reglock, flags);  in alchemy_clk_csrc_dis()
865 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_csrc_setp()  local
868 	spin_lock_irqsave(c->reglock, flags);  in alchemy_clk_csrc_setp()
869 	c->parent = index + 1;	/* value to write to register */  in alchemy_clk_csrc_setp()
870 	if (c->isen)  in alchemy_clk_csrc_setp()
871 		__alchemy_clk_csrc_en(c);  in alchemy_clk_csrc_setp()
872 	spin_unlock_irqrestore(c->reglock, flags);  in alchemy_clk_csrc_setp()
879 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_csrc_getp()  local
881 	return c->parent - 1;  in alchemy_clk_csrc_getp()
887 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_csrc_recalc()  local
888 	unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3;  in alchemy_clk_csrc_recalc()
890 	return parent_rate / c->dt[v];  in alchemy_clk_csrc_recalc()
896 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_csrc_setr()  local
906 	if ((d == 3) && (c->dt[2] != 3))  in alchemy_clk_csrc_setr()
910 		if (c->dt[i] == d)  in alchemy_clk_csrc_setr()
916 	spin_lock_irqsave(c->reglock, flags);  in alchemy_clk_csrc_setr()
917 	v = alchemy_rdsys(c->reg);  in alchemy_clk_csrc_setr()
918 	v &= ~(3 << c->shift);  in alchemy_clk_csrc_setr()
919 	v |= (i & 3) << c->shift;  in alchemy_clk_csrc_setr()
920 	alchemy_wrsys(v, c->reg);  in alchemy_clk_csrc_setr()
921 	spin_unlock_irqrestore(c->reglock, flags);  in alchemy_clk_csrc_setr()
929 	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);  in alchemy_clk_csrc_detr()  local
930 	int scale = c->dt[2] == 3 ? 1 : 2; /* au1300 check */  in alchemy_clk_csrc_detr()
953 static int alchemy_csrc_dt1[] = { 1, 4, 1, 2 };	/* rest */
954 static int alchemy_csrc_dt2[] = { 1, 4, 3, 2 };	/* Au1300 */
963 	struct clk *c;  in alchemy_clk_setup_imux()  local
1017 			a->parent = 1;  in alchemy_clk_setup_imux()
1020 			a->isen = 1;  in alchemy_clk_setup_imux()
1023 		c = clk_register(NULL, &a->hw);  in alchemy_clk_setup_imux()
1024 		if (IS_ERR(c))  in alchemy_clk_setup_imux()
1027 			clk_register_clkdev(c, id.name, NULL);  in alchemy_clk_setup_imux()
1049 	struct clk *c;  in alchemy_clk_init()  local
1052 	c = clk_register_fixed_rate(NULL, ALCHEMY_ROOT_CLK, NULL,  in alchemy_clk_init()
1054 	ERRCK(c)  in alchemy_clk_init()
1057 	c = alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK, ctype);  in alchemy_clk_init()
1058 	ERRCK(c)  in alchemy_clk_init()
1060 	/* AUXPLLs: max 1GHz on Au1300, 748MHz on older models */  in alchemy_clk_init()
1062 	c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK, ALCHEMY_AUXPLL_CLK,  in alchemy_clk_init()
1064 	ERRCK(c)  in alchemy_clk_init()
1067 		c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK,  in alchemy_clk_init()
1070 		ERRCK(c)  in alchemy_clk_init()
1074 	c = alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK);  in alchemy_clk_init()
1075 	ERRCK(c)  in alchemy_clk_init()
1078 	c = alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK);  in alchemy_clk_init()
1079 	ERRCK(c)  in alchemy_clk_init()
1082 	c = alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK, ctype);  in alchemy_clk_init()
1083 	ERRCK(c)  in alchemy_clk_init()
1086 	c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype);  in alchemy_clk_init()
1087 	ERRCK(c)  in alchemy_clk_init()