Lines Matching +full:quad +full:- +full:phase
1 # SPDX-License-Identifier: GPL-2.0
144 bool "Generic board-agnostic MIPS kernel"
286 Build a generic DT-based kernel image that boots on select
287 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
379 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
380 DECstation porting pages on <http://decstation.unix-ag.org/>.
444 Olivetti M700-10 workstations.
481 bool "Loongson 32-bit family of machines"
501 This enables support for the Loongson-1 family of machines.
503 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
508 bool "Loongson-2E/F family of machines"
511 This enables the support of early Loongson-2E/F family of machines.
514 bool "Loongson 64-bit family of machines"
549 This enables the support of Loongson-2/3 family of machines.
551 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
552 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
553 and Loongson-2F which will be removed), developed by the Institute
619 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
875 bool "Sibyte BCM91125C-CRhone"
885 bool "Sibyte BCM91125E-Rhone"
894 bool "Sibyte BCM91250A-SWARM"
907 bool "Sibyte BCM91250C2-LittleSur"
919 bool "Sibyte BCM91250E-Sentosa"
929 bool "Sibyte BCM91480B-BigSur"
978 The SNI RM200/300/400 are MIPS-based machines manufactured by
1057 This requires u-boot on the platform.
1073 source "arch/mips/sgi-ip27/Kconfig"
1076 source "arch/mips/cavium-octeon/Kconfig"
1354 bool "Loongson 64-bit CPU"
1378 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1380 Loongson-2E/2F is not covered here and will be removed in future.
1401 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1406 bool "Loongson 32-bit CPU"
1428 MIPS32 architecture. Most modern embedded systems with a 32-bit
1446 MIPS32 architecture. Most modern embedded systems with a 32-bit
1492 MIPS64 architecture. Many modern embedded systems with a 64-bit
1512 MIPS64 architecture. Many modern embedded systems with a 64-bit
1566 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
1567 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1569 cache, IOCU/IOMMU (though might be unused depending on the system-
1594 MIPS Technologies R4300-series processors.
1603 MIPS Technologies R4000-series processors other than 4300, including
1621 MIPS Technologies R5000-series processors other than the Nevada.
1630 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1640 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1651 MIPS Technologies R10000-series processors.
1715 bool "New Loongson-3 CPU Enhancements"
1719 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1720 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1721 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1722 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1727 please say 'N' here. If you want a high-performance kernel to run on
1728 new Loongson-3 machines only, please say 'Y' here.
1731 bool "Loongson-3 LLSC Workarounds"
1735 Loongson-3 processors have the llsc issues which require workarounds.
1745 Loongson-3A R4 and newer have the CPUCFG instruction available for
1748 cores, back to Loongson-3A1000.
1797 64-bit addressing which in turn makes the PTEs 64-bit in size.
1816 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1976 # CPU may reorder R->R, R->W, W->R, W->W
1984 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
2085 actually benefits from 64-bit processing or if your machine has
2087 menu if your system does not support both 32-bit and 64-bit kernels.
2090 bool "32-bit kernel"
2094 Select this option if you want to build a 32-bit kernel.
2097 bool "64-bit kernel"
2100 Select this option if you want to build a 64-bit kernel.
2125 This is only used if non-zero.
2152 # Support for a MIPS32 / MIPS64 style S-caches
2232 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2241 bool "Dynamic FPU affinity for FP-intensive threads"
2246 bool "MIPS R2-to-R6 emulator"
2251 Choose this option if you want to run non-R6 MIPS userland code.
2254 The only reason this is a build-time option is to save ~14K from the
2427 # CPU non-features
2432 # - The `daddi' instruction fails to trap on overflow.
2436 # - The `daddiu' instruction can produce an incorrect result.
2448 # - A double-word or a variable shift may give an incorrect result
2455 # - A double-word or a variable shift may give an incorrect result
2460 # - An integer division may give an incorrect result if started in
2470 # - A double-word or a variable shift may give an incorrect result
2497 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2545 # Workaround: do two phase flushing for Index_Invalidate_I
2549 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2551 # I-cache line worth of instructions being fetched may case spurious
2557 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2566 # - Highmem only makes sense for the 32-bit kernel.
2567 # - The current highmem code will only work properly on physically indexed
2574 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2598 This option must be set if a kernel might be executed on a MIPS16-
2600 words, it makes the kernel MIPS16-tolerant.
2619 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2687 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2688 EVA or 64-bit. The default is 16Mb.
2715 bool "Multi-Processing support"
2722 If you say N here, the kernel will run on uni- and multiprocessor
2731 See also the SMP-HOWTO available at
2737 bool "Support for hot-pluggable CPUs"
2771 int "Maximum number of CPUs (2-256)"
2781 kernel will support. The maximum supported value is 32 for 32-bit
2782 kernel and 64 for 64-bit kernels; the minimum value which makes
2786 This is purely to save memory - each supported CPU adds
2906 passed to the panic-ed kernel).
2909 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
2912 When this is enabled, the kernel will support use of 64-bit floating
2914 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
2915 32-bit MIPS systems this support is at the cost of increasing the
2918 will require 64-bit floating point, you may wish to reduce the size
2961 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
3056 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
3058 <http://www.linux-mips.org/wiki/DECstation>
3102 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3115 64-bit binaries using 32-bit quantities for addressing and certain
3116 data that would normally be 64-bit. They are used in special
3123 depends on $(cc-option,-mno-branch-likely)
3125 # https://github.com/llvm/llvm-project/issues/61045