Lines Matching +full:- +full:24
2 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2008-2009 PetaLogix
4 * Copyright (C) 2008 Jim Law - Iris LP All rights reserved.
21 * Input : Operand1 in Reg r5 - destination address
22 * Operand2 in Reg r6 - source address
23 * Operand3 in Reg r7 - number of bytes to transfer
24 * Output: Result in Reg r3 - starting destinaition address
44 cmpu r4, r4, r7 /* n = c - n (unsigned) */
51 /* n = 4 - n (yields 3, 2, 1 transfers for 1, 2, 3 addr offset) */
53 rsub r7, r4, r7 /* c = c - n adjust c */
63 addi r4, r4, -1 /* n-- (IN DELAY SLOT) */
67 cmpu r4, r4, r7 /* n = c - n (unsigned) */
73 rsub r7, r4, r7 /* c = c - n */
90 lwi r11, r6, 24 /* t3 = *(s + 24) */
94 swi r11, r5, 24 /* *(d + 24) = t3 */
97 addi r4, r4, -32 /* n = n - 32 */
107 addi r9, r9, -1
109 addi r9, r9, -1
113 bslli r11, r11, 24 /* h = h << 24 */
119 bslli r11, r12, 24 /* h = v << 24 */
124 bslli r11, r12, 24 /* h = v << 24 */
129 bslli r11, r12, 24 /* h = v << 24 */
134 bslli r11, r12, 24 /* h = v << 24 */
139 bslli r11, r12, 24 /* h = v << 24 */
140 lwi r12, r8, 24 /* v = *(as + 24) */
144 bslli r11, r12, 24 /* h = v << 24 */
148 swi r9, r5, 24 /* *(d + 24) = t1 */
149 bslli r11, r12, 24 /* h = v << 24 */
154 bslli r11, r12, 24 /* h = v << 24 */
156 addi r4, r4, -32 /* n = n - 32 */
165 bsrli r9, r12, 24 /* t1 = v >> 24 */
170 bsrli r9, r12, 24 /* t1 = v >> 24 */
175 bsrli r9, r12, 24 /* t1 = v >> 24 */
180 bsrli r9, r12, 24 /* t1 = v >> 24 */
185 bsrli r9, r12, 24 /* t1 = v >> 24 */
189 lwi r12, r8, 24 /* v = *(as + 24) */
190 bsrli r9, r12, 24 /* t1 = v >> 24 */
195 bsrli r9, r12, 24 /* t1 = v >> 24 */
197 swi r9, r5, 24 /* *(d + 24) = t1 */
200 bsrli r9, r12, 24 /* t1 = v >> 24 */
205 addi r4, r4, -32 /* n = n - 32 */
238 lwi r12, r8, 24 /* v = *(as + 24) */
246 swi r9, r5, 24 /* *(d + 24) = t1 */
254 addi r4, r4, -32 /* n = n - 32 */
260 cmpu r4, r4, r7 /* n = c - n (unsigned) */
274 addi r4, r4,-4 /* n-- */
285 addi r9, r9, -1
287 addi r9, r9, -1
291 bslli r11, r11, 24 /* h = h << 24 */
297 bslli r11, r12, 24 /* h = v << 24 */
298 addi r4, r4,-4 /* n = n - 4 */
308 bsrli r9, r12, 24 /* t1 = v >> 24 */
312 addi r4, r4,-4 /* n = n - 4 */
326 addi r4, r4,-4 /* n = n - 4 */
333 rsub r7, r10, r7 /* c = c - offset */
341 addi r7, r7, -1 /* c-- */
349 .size memcpy, . - memcpy
351 /*----------------------------------------------------------------------------*/
357 cmpu r4, r5, r6 /* n = s - d */
368 cmpu r4, r4, r7 /* n = c - n (unsigned) */
375 rsub r7, r4, r7 /* c = c - n adjust c */
380 addi r6, r6, -1 /* s-- */
381 addi r5, r5, -1 /* d-- */
385 addi r4, r4, -1 /* n-- (IN DELAY SLOT) */
389 cmpu r4, r4, r7 /* n = c - n (unsigned) */
395 rsub r7, r4, r7 /* c = c - n */
402 addi r6, r6, -32 /* s = s - 32 */
403 addi r5, r5, -32 /* d = d - 32 */
405 lwi r10, r6, 24 /* t2 = *(s + 24) */
409 swi r10, r5, 24 /* *(d + 24) = t2 */
419 addi r4, r4, -32 /* n = n - 32 */
426 rsub r6, r4, r6 /* s = s - n */
429 addi r9, r9, -1
431 addi r9, r9, -1
437 addi r8, r8, -32 /* as = as - 32 */
438 addi r5, r5, -32 /* d = d - 32 */
440 bslli r9, r12, 24 /* t1 = v << 24 */
444 lwi r12, r8, 24 /* v = *(as + 24) */
445 bslli r9, r12, 24 /* t1 = v << 24 */
447 swi r9, r5, 24 /* *(d + 24) = t1 */
450 bslli r9, r12, 24 /* t1 = v << 24 */
455 bslli r9, r12, 24 /* t1 = v << 24 */
460 bslli r9, r12, 24 /* t1 = v << 24 */
465 bslli r9, r12, 24 /* t1 = v << 24 */
470 bslli r9, r12, 24 /* t1 = v << 24 */
475 bslli r9, r12, 24 /* t1 = v << 24 */
478 addi r4, r4, -32 /* n = n - 32 */
484 bsrli r11, r11, 24 /* h = h >> 24 */
486 addi r8, r8, -32 /* as = as - 32 */
487 addi r5, r5, -32 /* d = d - 32 */
492 bsrli r11, r12, 24 /* h = v >> 24 */
493 lwi r12, r8, 24 /* v = *(as + 24) */
496 swi r9, r5, 24 /* *(d + 24) = t1 */
497 bsrli r11, r12, 24 /* h = v >> 24 */
502 bsrli r11, r12, 24 /* h = v >> 24 */
507 bsrli r11, r12, 24 /* h = v >> 24 */
512 bsrli r11, r12, 24 /* h = v >> 24 */
517 bsrli r11, r12, 24 /* h = v >> 24 */
522 bsrli r11, r12, 24 /* h = v >> 24 */
527 addi r4, r4, -32 /* n = n - 32 */
529 bsrli r11, r12, 24 /* h = v >> 24 (IN DELAY SLOT) */
535 addi r8, r8, -32 /* as = as - 32 */
536 addi r5, r5, -32 /* d = d - 32 */
542 lwi r12, r8, 24 /* v = *(as + 24) */
545 swi r9, r5, 24 /* *(d + 24) = t1 */
576 addi r4, r4, -32 /* n = n - 32 */
582 cmpu r4, r4, r7 /* n = c - n (unsigned) */
587 rsub r5, r4, r5 /* d = d - n */
588 rsub r6, r4, r6 /* s = s - n */
589 rsub r7, r4, r7 /* c = c - n */
596 addi r4, r4,-4 /* n-- */
607 addi r9, r9, -1
609 addi r9, r9, -1
615 addi r4, r4,-4 /* n = n - 4 */
617 bslli r9, r12, 24 /* t1 = v << 24 */
626 bsrli r11, r11, 24 /* h = h >> 24 */
628 addi r4, r4,-4 /* n = n - 4 */
634 bsrli r11, r12, 24 /* h = v >> 24 (IN DELAY SLOT) */
641 addi r4, r4,-4 /* n = n - 4 */
654 addi r6, r6, -1 /* s-- */
656 addi r5, r5, -1 /* d-- */
659 addi r7, r7, -1 /* c-- (IN DELAY SLOT) */
665 .size memmove, . - memmove