2  * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
3  * Copyright (C) 2012-2013 Xilinx, Inc.
4  * Copyright (C) 2007-2009 PetaLogix
36 #define TCSR_MDT	(1<<0)
37 #define TCSR_UDT	(1<<1)
38 #define TCSR_GENT	(1<<2)
39 #define TCSR_CAPT	(1<<3)
40 #define TCSR_ARHT	(1<<4)
41 #define TCSR_LOAD	(1<<5)
42 #define TCSR_ENIT	(1<<6)
43 #define TCSR_ENT	(1<<7)
44 #define TCSR_TINT	(1<<8)
45 #define TCSR_PWMA	(1<<9)
46 #define TCSR_ENALL	(1<<10)
80 		load_val = 1;  in xilinx_timer0_start_periodic()
81 	/* loading value to timer reg */  in xilinx_timer0_start_periodic()
87 	/* see timer data sheet for detail  in xilinx_timer0_start_periodic()
88 	 * !ENALL - don't enable 'em all  in xilinx_timer0_start_periodic()
89 	 * !PWMA - disable pwm  in xilinx_timer0_start_periodic()
90 	 * TINT - clear interrupt status  in xilinx_timer0_start_periodic()
91 	 * ENT- enable timer itself  in xilinx_timer0_start_periodic()
92 	 * ENIT - enable interrupt  in xilinx_timer0_start_periodic()
93 	 * !LOAD - clear the bit to let go  in xilinx_timer0_start_periodic()
94 	 * ARHT - auto reload  in xilinx_timer0_start_periodic()
95 	 * !CAPT - no external trigger  in xilinx_timer0_start_periodic()
96 	 * !GENT - no external signal  in xilinx_timer0_start_periodic()
97 	 * UDT - set the timer as down counter  in xilinx_timer0_start_periodic()
98 	 * !MDT0 - generate mode  in xilinx_timer0_start_periodic()
107 		load_val = 1;  in xilinx_timer0_start_oneshot()
108 	/* loading value to timer reg */  in xilinx_timer0_start_oneshot()
160 	evt->event_handler(evt);  in timer_interrupt()
173 		clockevent_delta2ns(1, &clockevent_xilinx_timer);  in xilinx_clockevent_init()
174 	clockevent_xilinx_timer.min_delta_ticks = 1;  in xilinx_clockevent_init()
188 	/* reading actual value of timer 1 */  in xilinx_read()
239 	/* start timer1 - up counting without interrupt */  in xilinx_clocksource_init()
242 	/* register timecounter - for ftrace support */  in xilinx_clocksource_init()
246 static int __init xilinx_timer_init(struct device_node *timer)  in xilinx_timer_init()  argument
251 	u32 timer_num = 1;  in xilinx_timer_init()
254 	/* If this property is present, the device is a PWM and not a timer */  in xilinx_timer_init()
255 	if (of_property_read_bool(timer, "#pwm-cells"))  in xilinx_timer_init()
259 		return -EINVAL;  in xilinx_timer_init()
261 	initialized = 1;  in xilinx_timer_init()
263 	timer_baseaddr = of_iomap(timer, 0);  in xilinx_timer_init()
265 		pr_err("ERROR: invalid timer base address\n");  in xilinx_timer_init()
266 		return -ENXIO;  in xilinx_timer_init()
278 	irq = irq_of_parse_and_map(timer, 0);  in xilinx_timer_init()
281 		return -EINVAL;  in xilinx_timer_init()
284 	of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num);  in xilinx_timer_init()
287 		return -EINVAL;  in xilinx_timer_init()
290 	pr_info("%pOF: irq=%d\n", timer, irq);  in xilinx_timer_init()
292 	clk = of_clk_get(timer, 0);  in xilinx_timer_init()
294 		pr_err("ERROR: timer CCF input clock not found\n");  in xilinx_timer_init()
295 		/* If there is clock-frequency property than use it */  in xilinx_timer_init()
296 		of_property_read_u32(timer, "clock-frequency",  in xilinx_timer_init()
309 	ret = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer",  in xilinx_timer_init()
329 TIMER_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a",