Lines Matching +full:self +full:- +full:working +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
8 * Copyright (C) 2008-2009 PetaLogix
13 * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
18 * Low-level exception handers, MMU support, and rewrite.
21 * Copyright (C) 1998-1999 TiVo, Inc.
39 * and do all processing in real mode. All what they need is a valid current
43 * The handlers which require translation are in entry.S --KAA
46 * - Non self-modifying exception handler for the following exception conditions
47 * - Unalignment
48 * - Instruction bus error
49 * - Data bus error
50 * - Illegal instruction opcode
51 * - Divide-by-zero
53 * - Privileged instruction exception (MMU)
54 * - Data storage exception (MMU)
55 * - Instruction storage exception (MMU)
56 * - Data TLB miss exception (MMU)
57 * - Instruction TLB miss exception (MMU)
60 * possibly get multiple re-entrancy if interrupt handles themselves cause
76 #include <asm/asm-offsets.h>
141 /* Only the used shift constants defined here - add more if needed */
193 * hw_exception_handler - Handler for exceptions
196 * - Handles all exceptions
197 * - Does not handle unaligned exceptions during load into r17, r1, r0.
198 * - Does not handle unaligned exceptions during store from r17 (cannot be
203 * EAR - |----|----|----|----|----|----|----|----|
204 * - < ## 32 bit faulting address ## >
206 * ESR - |----|----|----|----|----| - | - |-----|-----|
207 * - W S REG EXC
211 * ----------------------------------------
213 * +-------------+ + 0
215 * +-------------+ + 4
222 * +-------------+ + 76
227 * which is used for storing register values - noMMu style was, that values were
264 /* 0 - Undefined */
266 /* 1 - Unaligned data access exception */
268 /* 2 - Illegal op-code exception */
270 /* 3 - Instruction bus error exception */
272 /* 4 - Data bus error exception */
274 /* 5 - Divide by zero exception */
276 /* 6 - Floating point unit exception */
278 /* 7 - Privileged instruction exception */
280 /* 8 - 15 - Undefined */
289 /* 16 - Data storage exception */
291 /* 17 - Instruction storage exception */
293 /* 18 - Data TLB miss exception */
295 /* 19 - Instruction TLB miss exception */
297 /* 20 - 31 - Undefined */
361 /* 0x01 - Unaligned data access exception
363 * or when a 16-bit access is not aligned on a 16-bit boundary.
369 /* Working registers already saved: R3, R4, R5, R6
375 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
397 /* Load a word, byte-by-byte from destination address
411 /* Load a half-word, byte-by-byte from destination
444 /* Get the word - delay slot */
446 /* Store the word, byte-by-byte into destination address */
458 /* Store the lower half-word, byte-by-byte into destination address */
476 /* 0x10 - Data Storage Exception
483 /* Working registers already saved: R3, R4, R5, R6
495 * tried to access a kernel or read-protected page - always
498 andi r4, r4, ESR_DIZ /* ESR_Z - zone protection */
509 * tried to access a kernel or read-protected page - always
520 bsrli r5, r3, PGDIR_SHIFT - 2
521 andi r5, r5, PAGE_SIZE - 4
530 andi r6, r6, PAGE_SIZE - 4
542 * We set ZSEL, where only the LS-bit determines user access.
545 * If shared is set, we cause a zero PID->TID load.
572 /* The bailout. Restore registers to pre-exception conditions
581 /* 0x11 - Instruction Storage Exception
582 * This is caused by a fetch from non-execute or guarded pages. */
584 /* Working registers already saved: R3, R4, R5, R6
591 /* 0x12 - Data TLB Miss Exception
597 /* Working registers already saved: R3, R4, R5, R6
621 bsrli r5, r3, PGDIR_SHIFT - 2
622 andi r5, r5, PAGE_SIZE - 4
631 andi r6, r6, PAGE_SIZE - 4
642 * We set ZSEL, where only the LS-bit determines user access.
645 * If shared is set, we cause a zero PID->TID load.
653 /* The bailout. Restore registers to pre-exception conditions
662 /* 0x13 - Instruction TLB Miss Exception
667 /* Working registers already saved: R3, R4, R5, R6
692 bsrli r5, r3, PGDIR_SHIFT - 2
693 andi r5, r5, PAGE_SIZE - 4
702 andi r6, r6, PAGE_SIZE - 4
713 * We set ZSEL, where only the LS-bit determines user access.
716 * If shared is set, we cause a zero PID->TID load.
724 /* The bailout. Restore registers to pre-exception conditions
734 * r3 - EA of fault
735 * r4 - TLB LO (info from Linux PTE)
736 * r5, r6 - available to use
737 * PID - loaded with proper value when we get here
753 addik r5, r5, 1 /* MS: inc tlb_index -> use next one */
756 andi r5, r5, MICROBLAZE_TLB_SIZE - 1
799 /* At present, this routine just hangs. - extern void abort(void) */
817 * When this is called, we are in virtual mode with exceptions enabled
818 * and registers 1-13,15,17,18 saved.
833 andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
836 load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
837 /* Load a word, byte-by-byte from destination address and save it in tmp space*/
847 /* Get the destination register value into r3 - delay slot */
850 /* Load a half-word, byte-by-byte from destination address and
870 swi r3, r5, 0; /* Get the word - delay slot */
871 /* Store the word, byte-by-byte into destination address */
882 /* Store the lower half-word, byte-by-byte into destination address */
906 addik r6, r6, -4 /* for finding proper fixup */
911 addik r15, r0, ret_from_exc-8 /* setup return address */
933 /* FIXME add handle function for unhandled exception - dump register */
938 * - Contains code snippets for each register that caused the unalign exception
939 * - Hence exception handler is NOT self-modifying
940 * - Separate table for load exceptions and store exceptions.
941 * - Each table is of size: (8 * 32) = 256 bytes