Lines Matching refs:PTO
180 swi r2, r1, PTO+PT_R2; /* Save SDA */ \
181 swi r3, r1, PTO+PT_R3; \
182 swi r4, r1, PTO+PT_R4; \
183 swi r5, r1, PTO+PT_R5; \
184 swi r6, r1, PTO+PT_R6; \
185 swi r7, r1, PTO+PT_R7; \
186 swi r8, r1, PTO+PT_R8; \
187 swi r9, r1, PTO+PT_R9; \
188 swi r10, r1, PTO+PT_R10; \
189 swi r11, r1, PTO+PT_R11; /* save clobbered regs after rval */\
190 swi r12, r1, PTO+PT_R12; \
191 swi r13, r1, PTO+PT_R13; /* Save SDA2 */ \
192 swi r14, r1, PTO+PT_PC; /* PC, before IRQ/trap */ \
193 swi r15, r1, PTO+PT_R15; /* Save LP */ \
194 swi r16, r1, PTO+PT_R16; \
195 swi r17, r1, PTO+PT_R17; \
196 swi r18, r1, PTO+PT_R18; /* Save asm scratch reg */ \
197 swi r19, r1, PTO+PT_R19; \
198 swi r20, r1, PTO+PT_R20; \
199 swi r21, r1, PTO+PT_R21; \
200 swi r22, r1, PTO+PT_R22; \
201 swi r23, r1, PTO+PT_R23; \
202 swi r24, r1, PTO+PT_R24; \
203 swi r25, r1, PTO+PT_R25; \
204 swi r26, r1, PTO+PT_R26; \
205 swi r27, r1, PTO+PT_R27; \
206 swi r28, r1, PTO+PT_R28; \
207 swi r29, r1, PTO+PT_R29; \
208 swi r30, r1, PTO+PT_R30; \
209 swi r31, r1, PTO+PT_R31; /* Save current task reg */ \
211 swi r11, r1, PTO+PT_MSR;
214 lwi r2, r1, PTO+PT_R2; /* restore SDA */ \
215 lwi r3, r1, PTO+PT_R3; \
216 lwi r4, r1, PTO+PT_R4; \
217 lwi r5, r1, PTO+PT_R5; \
218 lwi r6, r1, PTO+PT_R6; \
219 lwi r7, r1, PTO+PT_R7; \
220 lwi r8, r1, PTO+PT_R8; \
221 lwi r9, r1, PTO+PT_R9; \
222 lwi r10, r1, PTO+PT_R10; \
223 lwi r11, r1, PTO+PT_R11; /* restore clobbered regs after rval */\
224 lwi r12, r1, PTO+PT_R12; \
225 lwi r13, r1, PTO+PT_R13; /* restore SDA2 */ \
226 lwi r14, r1, PTO+PT_PC; /* RESTORE_LINK PC, before IRQ/trap */\
227 lwi r15, r1, PTO+PT_R15; /* restore LP */ \
228 lwi r16, r1, PTO+PT_R16; \
229 lwi r17, r1, PTO+PT_R17; \
230 lwi r18, r1, PTO+PT_R18; /* restore asm scratch reg */ \
231 lwi r19, r1, PTO+PT_R19; \
232 lwi r20, r1, PTO+PT_R20; \
233 lwi r21, r1, PTO+PT_R21; \
234 lwi r22, r1, PTO+PT_R22; \
235 lwi r23, r1, PTO+PT_R23; \
236 lwi r24, r1, PTO+PT_R24; \
237 lwi r25, r1, PTO+PT_R25; \
238 lwi r26, r1, PTO+PT_R26; \
239 lwi r27, r1, PTO+PT_R27; \
240 lwi r28, r1, PTO+PT_R28; \
241 lwi r29, r1, PTO+PT_R29; \
242 lwi r30, r1, PTO+PT_R30; \
243 lwi r31, r1, PTO+PT_R31; /* Restore cur task reg */
246 lwi r11, r1, PTO+PT_MSR; \
251 lwi r11, r1, PTO+PT_MSR; \
272 swi r1, r1, PTO+PT_MODE; \
285 swi r11, r1, PTO+PT_R1; /* Store user SP. */ \
286 swi r0, r1, PTO+PT_MODE; /* Was in user-mode. */ \
356 swi r0, r1, PTO+PT_R3
357 swi r0, r1, PTO+PT_R4
359 swi r0, r1, PTO+PT_MODE; /* Was in user-mode. */
361 swi r11, r1, PTO+PT_R1; /* Store user SP. */
365 swi r12, r1, PTO+PT_R0;
384 swi r3, r1, PTO+PT_R3
386 addik r5, r1, PTO+PT_R0
390 lwi r5, r1, PTO+PT_R5;
391 lwi r6, r1, PTO+PT_R6;
392 lwi r7, r1, PTO+PT_R7;
393 lwi r8, r1, PTO+PT_R8;
394 lwi r9, r1, PTO+PT_R9;
395 lwi r10, r1, PTO+PT_R10;
436 swi r3, r1, PTO+PT_R3
437 swi r4, r1, PTO+PT_R4
445 lwi r11, r1, PTO+PT_MODE;
457 addik r5, r1, PTO+PT_R0
476 addik r5, r1, PTO; /* Arg 1: struct pt_regs *regs */
542 addik r5, r1, PTO; /* add user context as 1st arg */
553 swi r17, r1, PTO+PT_PC;
563 addik r5, r1, PTO /* parameter struct pt_regs * regs */
589 swi r17, r1, PTO+PT_PC;
596 addik r7, r1, PTO /* parameter struct pt_regs * regs */
619 swi r17, r1, PTO+PT_PC;
626 addik r5, r1, PTO /* parameter struct pt_regs * regs */
631 swi r17, r1, PTO+PT_PC;
638 addik r5, r1, PTO /* parameter struct pt_regs * regs */
642 lwi r11, r1, PTO+PT_MODE;
674 addik r5, r1, PTO; /* Arg 1: struct pt_regs *regs */
731 swi r1, r1, PTO+PT_MODE; /* 0 - user mode, 1 - kernel mode */
744 swi r0, r1, PTO+PT_MODE;
746 swi r11, r1, PTO+PT_R1;
753 addik r5, r1, PTO;
757 lwi r11, r1, PTO+PT_MODE;
773 addik r5, r1, PTO; /* Arg 1: struct pt_regs *regs */
828 lwi r2, r1, PTO+PT_MSR
833 lwi r2, r1, PTO+PT_PID
836 lwi r2, r1, PTO+PT_TLBI
839 lwi r2, r1, PTO+PT_ZPR
843 lwi r2, r1, PTO+PT_FSR
849 addik r6, r0, PTO+PT_TLBL0
850 addik r7, r0, PTO+PT_TLBH0
876 lwi r14, r1, PTO+PT_R14
877 lwi r16, r1, PTO+PT_PC
896 swi r14, r1, PTO+PT_R14 /* rewrite saved R14 value */
897 swi r16, r1, PTO+PT_PC; /* PC and r16 are the same */
911 swi r2, r1, PTO+PT_PID
914 swi r2, r1, PTO+PT_TLBI
917 swi r2, r1, PTO+PT_ZPR
921 swi r2, r1, PTO+PT_FSR
924 swi r2, r1, PTO+PT_MSR
928 addik r6, r0, PTO+PT_TLBL0
929 addik r7, r0, PTO+PT_TLBH0
989 swi r0, r1, PTO+PT_R0; /* R0 must be saved too */
990 swi r14, r1, PTO+PT_R14 /* rewrite saved R14 value */
991 swi r16, r1, PTO+PT_PC; /* PC and r16 are the same */
994 swi r11, r1, PTO+PT_EAR;
996 swi r11, r1, PTO+PT_ESR;
998 swi r11, r1, PTO+PT_FSR;
1003 swi r11, r1, PTO+PT_R1
1007 addi r5, r1, PTO /* pass pt_reg address as the first arg */
1025 swi r16, r1, PTO+PT_PC; /* Save LP */
1026 swi r0, r1, PTO+PT_MODE; /* Was in user-mode. */
1028 swi r11, r1, PTO+PT_R1; /* Store user SP. */
1032 addik r5, r1, PTO;
1040 lwi r11, r1, PTO+PT_MODE;
1059 addik r5, r1, PTO; /* Arg 1: struct pt_regs *regs */
1081 lwi r14, r1, PTO+PT_R14;
1082 lwi r16, r1, PTO+PT_PC;