Lines Matching +full:0 +full:x1e000000
13 #define PVR_MSR_BIT 0x400
22 #define PVR0_PVR_FULL_MASK 0x80000000
23 #define PVR0_USE_BARREL_MASK 0x40000000
24 #define PVR0_USE_DIV_MASK 0x20000000
25 #define PVR0_USE_HW_MUL_MASK 0x10000000
26 #define PVR0_USE_FPU_MASK 0x08000000
27 #define PVR0_USE_EXC_MASK 0x04000000
28 #define PVR0_USE_ICACHE_MASK 0x02000000
29 #define PVR0_USE_DCACHE_MASK 0x01000000
30 #define PVR0_USE_MMU 0x00800000
31 #define PVR0_USE_BTC 0x00400000
32 #define PVR0_ENDI 0x00200000
33 #define PVR0_VERSION_MASK 0x0000FF00
34 #define PVR0_USER1_MASK 0x000000FF
37 #define PVR1_USER2_MASK 0xFFFFFFFF
40 #define PVR2_D_OPB_MASK 0x80000000 /* or AXI */
41 #define PVR2_D_LMB_MASK 0x40000000
42 #define PVR2_I_OPB_MASK 0x20000000 /* or AXI */
43 #define PVR2_I_LMB_MASK 0x10000000
44 #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
45 #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
46 #define PVR2_D_PLB_MASK 0x02000000 /* new */
47 #define PVR2_I_PLB_MASK 0x01000000 /* new */
48 #define PVR2_INTERCONNECT 0x00800000 /* new */
49 #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
50 #define PVR2_USE_FSL_EXC 0x00040000 /* new */
51 #define PVR2_USE_MSR_INSTR 0x00020000
52 #define PVR2_USE_PCMP_INSTR 0x00010000
53 #define PVR2_AREA_OPTIMISED 0x00008000
54 #define PVR2_USE_BARREL_MASK 0x00004000
55 #define PVR2_USE_DIV_MASK 0x00002000
56 #define PVR2_USE_HW_MUL_MASK 0x00001000
57 #define PVR2_USE_FPU_MASK 0x00000800
58 #define PVR2_USE_MUL64_MASK 0x00000400
59 #define PVR2_USE_FPU2_MASK 0x00000200 /* new */
60 #define PVR2_USE_IPLBEXC 0x00000100
61 #define PVR2_USE_DPLBEXC 0x00000080
62 #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
63 #define PVR2_UNALIGNED_EXC_MASK 0x00000020
64 #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
65 #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 /* or AXI */
66 #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 /* or AXI */
67 #define PVR2_DIV_ZERO_EXC_MASK 0x00000002
68 #define PVR2_FPU_EXC_MASK 0x00000001
71 #define PVR3_DEBUG_ENABLED_MASK 0x80000000
72 #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
73 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
74 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
75 #define PVR3_FSL_LINKS_MASK 0x00000380
78 #define PVR4_USE_ICACHE_MASK 0x80000000 /* ICU */
79 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* ICTS */
80 #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 /* ICW */
81 #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 /* ICLL */
82 #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 /* ICBS */
83 #define PVR4_ICACHE_ALWAYS_USED 0x00008000 /* IAU */
84 #define PVR4_ICACHE_INTERFACE 0x00002000 /* ICI */
87 #define PVR5_USE_DCACHE_MASK 0x80000000 /* DCU */
88 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* DCTS */
89 #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 /* DCW */
90 #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 /* DCLL */
91 #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 /* DCBS */
92 #define PVR5_DCACHE_ALWAYS_USED 0x00008000 /* DAU */
93 #define PVR5_DCACHE_USE_WRITEBACK 0x00004000 /* DWB */
94 #define PVR5_DCACHE_INTERFACE 0x00002000 /* DCI */
97 #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
100 #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
103 #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
106 #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
109 #define PVR10_TARGET_FAMILY_MASK 0xFF000000
112 #define PVR11_USE_MMU 0xC0000000
113 #define PVR11_MMU_ITLB_SIZE 0x38000000
114 #define PVR11_MMU_DTLB_SIZE 0x07000000
115 #define PVR11_MMU_TLB_ACCESS 0x00C00000
116 #define PVR11_MMU_ZONES 0x003C0000
117 #define PVR11_MMU_PRIVINS 0x00010000
119 #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
122 #define PVR_IS_FULL(_pvr) (_pvr.pvr[0] & PVR0_PVR_FULL_MASK)
123 #define PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & PVR0_USE_BARREL_MASK)
124 #define PVR_USE_DIV(_pvr) (_pvr.pvr[0] & PVR0_USE_DIV_MASK)
125 #define PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)
126 #define PVR_USE_FPU(_pvr) (_pvr.pvr[0] & PVR0_USE_FPU_MASK)
128 #define PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_ICACHE_MASK)
129 #define PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_DCACHE_MASK)
130 #define PVR_VERSION(_pvr) ((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)
131 #define PVR_USER1(_pvr) (_pvr.pvr[0] & PVR0_USER1_MASK)
219 #define PVR_ENDIAN(_pvr) (_pvr.pvr[0] & PVR0_ENDI)