Lines Matching +full:tri +full:- +full:default +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek
13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
16 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 stdout-path = "/plb@0/serial@84000000";
35 #address-cells = <1>;
37 #size-cells = <0>;
39 clock-frequency = <125000000>;
40 compatible = "xlnx,microblaze-7.10.d";
41 d-cache-baseaddr = <0x90000000>;
42 d-cache-highaddr = <0x9fffffff>;
43 d-cache-line-size = <0x10>;
44 d-cache-size = <0x2000>;
46 i-cache-baseaddr = <0x90000000>;
47 i-cache-highaddr = <0x9fffffff>;
48 i-cache-line-size = <0x10>;
49 i-cache-size = <0x2000>;
52 timebase-frequency = <125000000>;
53 xlnx,addr-tag-bits = <0xf>;
54 xlnx,allow-dcache-wr = <0x1>;
55 xlnx,allow-icache-wr = <0x1>;
56 xlnx,area-optimized = <0x0>;
57 xlnx,cache-byte-size = <0x2000>;
58 xlnx,d-lmb = <0x1>;
59 xlnx,d-opb = <0x0>;
60 xlnx,d-plb = <0x1>;
61 xlnx,data-size = <0x20>;
62 xlnx,dcache-addr-tag = <0xf>;
63 xlnx,dcache-always-used = <0x1>;
64 xlnx,dcache-byte-size = <0x2000>;
65 xlnx,dcache-line-len = <0x4>;
66 xlnx,dcache-use-fsl = <0x1>;
67 xlnx,debug-enabled = <0x1>;
68 xlnx,div-zero-exception = <0x1>;
69 xlnx,dopb-bus-exception = <0x0>;
70 xlnx,dynamic-bus-sizing = <0x1>;
71 xlnx,edge-is-positive = <0x1>;
74 xlnx,fpu-exception = <0x1>;
75 xlnx,fsl-data-size = <0x20>;
76 xlnx,fsl-exception = <0x0>;
77 xlnx,fsl-links = <0x0>;
78 xlnx,i-lmb = <0x1>;
79 xlnx,i-opb = <0x0>;
80 xlnx,i-plb = <0x1>;
81 xlnx,icache-always-used = <0x1>;
82 xlnx,icache-line-len = <0x4>;
83 xlnx,icache-use-fsl = <0x1>;
84 xlnx,ill-opcode-exception = <0x1>;
87 xlnx,interrupt-is-edge = <0x0>;
88 xlnx,iopb-bus-exception = <0x0>;
89 xlnx,mmu-dtlb-size = <0x4>;
90 xlnx,mmu-itlb-size = <0x2>;
91 xlnx,mmu-tlb-access = <0x3>;
92 xlnx,mmu-zones = <0x10>;
93 xlnx,number-of-pc-brk = <0x1>;
94 xlnx,number-of-rd-addr-brk = <0x0>;
95 xlnx,number-of-wr-addr-brk = <0x0>;
96 xlnx,opcode-0x0-illegal = <0x1>;
98 xlnx,pvr-user1 = <0x0>;
99 xlnx,pvr-user2 = <0x0>;
100 xlnx,reset-msr = <0x0>;
102 xlnx,unaligned-exceptions = <0x1>;
103 xlnx,use-barrel = <0x1>;
104 xlnx,use-dcache = <0x1>;
105 xlnx,use-div = <0x1>;
106 xlnx,use-ext-brk = <0x1>;
107 xlnx,use-ext-nm-brk = <0x1>;
108 xlnx,use-extended-fsl-instr = <0x0>;
109 xlnx,use-fpu = <0x2>;
110 xlnx,use-hw-mul = <0x2>;
111 xlnx,use-icache = <0x1>;
112 xlnx,use-interrupt = <0x1>;
113 xlnx,use-mmu = <0x3>;
114 xlnx,use-msr-instr = <0x1>;
115 xlnx,use-pcmp-instr = <0x1>;
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
124 bank-width = <2>;
125 compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
128 xlnx,include-datawidth-matching-0 = <0x1>;
129 xlnx,include-datawidth-matching-1 = <0x0>;
130 xlnx,include-datawidth-matching-2 = <0x0>;
131 xlnx,include-datawidth-matching-3 = <0x0>;
132 xlnx,include-negedge-ioregs = <0x0>;
133 xlnx,include-plb-ipif = <0x1>;
134 xlnx,include-wrbuf = <0x1>;
135 xlnx,max-mem-width = <0x10>;
136 xlnx,mch-native-dwidth = <0x20>;
137 xlnx,mch-plb-clk-period-ps = <0x1f40>;
138 xlnx,mch-splb-awidth = <0x20>;
139 xlnx,mch0-accessbuf-depth = <0x10>;
140 xlnx,mch0-protocol = <0x0>;
141 xlnx,mch0-rddatabuf-depth = <0x10>;
142 xlnx,mch1-accessbuf-depth = <0x10>;
143 xlnx,mch1-protocol = <0x0>;
144 xlnx,mch1-rddatabuf-depth = <0x10>;
145 xlnx,mch2-accessbuf-depth = <0x10>;
146 xlnx,mch2-protocol = <0x0>;
147 xlnx,mch2-rddatabuf-depth = <0x10>;
148 xlnx,mch3-accessbuf-depth = <0x10>;
149 xlnx,mch3-protocol = <0x0>;
150 xlnx,mch3-rddatabuf-depth = <0x10>;
151 xlnx,mem0-width = <0x10>;
152 xlnx,mem1-width = <0x20>;
153 xlnx,mem2-width = <0x20>;
154 xlnx,mem3-width = <0x20>;
155 xlnx,num-banks-mem = <0x1>;
156 xlnx,num-channels = <0x0>;
157 xlnx,priority-mode = <0x0>;
158 xlnx,synch-mem-0 = <0x0>;
159 xlnx,synch-mem-1 = <0x0>;
160 xlnx,synch-mem-2 = <0x0>;
161 xlnx,synch-mem-3 = <0x0>;
162 xlnx,synch-pipedelay-0 = <0x2>;
163 xlnx,synch-pipedelay-1 = <0x2>;
164 xlnx,synch-pipedelay-2 = <0x2>;
165 xlnx,synch-pipedelay-3 = <0x2>;
166 xlnx,tavdv-ps-mem-0 = <0x1adb0>;
167 xlnx,tavdv-ps-mem-1 = <0x3a98>;
168 xlnx,tavdv-ps-mem-2 = <0x3a98>;
169 xlnx,tavdv-ps-mem-3 = <0x3a98>;
170 xlnx,tcedv-ps-mem-0 = <0x1adb0>;
171 xlnx,tcedv-ps-mem-1 = <0x3a98>;
172 xlnx,tcedv-ps-mem-2 = <0x3a98>;
173 xlnx,tcedv-ps-mem-3 = <0x3a98>;
174 xlnx,thzce-ps-mem-0 = <0x88b8>;
175 xlnx,thzce-ps-mem-1 = <0x1b58>;
176 xlnx,thzce-ps-mem-2 = <0x1b58>;
177 xlnx,thzce-ps-mem-3 = <0x1b58>;
178 xlnx,thzoe-ps-mem-0 = <0x1b58>;
179 xlnx,thzoe-ps-mem-1 = <0x1b58>;
180 xlnx,thzoe-ps-mem-2 = <0x1b58>;
181 xlnx,thzoe-ps-mem-3 = <0x1b58>;
182 xlnx,tlzwe-ps-mem-0 = <0x88b8>;
183 xlnx,tlzwe-ps-mem-1 = <0x0>;
184 xlnx,tlzwe-ps-mem-2 = <0x0>;
185 xlnx,tlzwe-ps-mem-3 = <0x0>;
186 xlnx,twc-ps-mem-0 = <0x2af8>;
187 xlnx,twc-ps-mem-1 = <0x3a98>;
188 xlnx,twc-ps-mem-2 = <0x3a98>;
189 xlnx,twc-ps-mem-3 = <0x3a98>;
190 xlnx,twp-ps-mem-0 = <0x11170>;
191 xlnx,twp-ps-mem-1 = <0x2ee0>;
192 xlnx,twp-ps-mem-2 = <0x2ee0>;
193 xlnx,twp-ps-mem-3 = <0x2ee0>;
194 xlnx,xcl0-linesize = <0x4>;
195 xlnx,xcl0-writexfer = <0x1>;
196 xlnx,xcl1-linesize = <0x4>;
197 xlnx,xcl1-writexfer = <0x1>;
198 xlnx,xcl2-linesize = <0x4>;
199 xlnx,xcl2-writexfer = <0x1>;
200 xlnx,xcl3-linesize = <0x4>;
201 xlnx,xcl3-writexfer = <0x1>;
203 Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
204 #address-cells = <1>;
205 #size-cells = <1>;
209 compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
210 interrupt-parent = <&xps_intc_0>;
211 interrupts = < 5 2 >;
212 llink-connected = <&PIM3>;
213 local-mac-address = [ 00 0a 35 00 00 00 ];
215 xlnx,bus2core-clk-ratio = <0x1>;
216 xlnx,phy-type = <0x1>;
220 xlnx,temac-type = <0x0>;
226 compatible = "xlnx,xps-iic-2.00.a";
227 interrupt-parent = <&xps_intc_0>;
228 interrupts = < 6 2 >;
230 xlnx,clk-freq = <0x7735940>;
232 xlnx,gpo-width = <0x1>;
233 xlnx,iic-freq = <0x186a0>;
234 xlnx,scl-inertial-delay = <0x0>;
235 xlnx,sda-inertial-delay = <0x0>;
236 xlnx,ten-bit-adr = <0x0>;
239 compatible = "xlnx,xps-gpio-1.00.a";
240 interrupt-parent = <&xps_intc_0>;
241 interrupts = < 7 2 >;
243 xlnx,all-inputs = <0x0>;
244 xlnx,all-inputs-2 = <0x0>;
245 xlnx,dout-default = <0x0>;
246 xlnx,dout-default-2 = <0x0>;
248 xlnx,gpio-width = <0x8>;
249 xlnx,interrupt-present = <0x1>;
250 xlnx,is-bidir = <0x1>;
251 xlnx,is-bidir-2 = <0x1>;
252 xlnx,is-dual = <0x0>;
253 xlnx,tri-default = <0xffffffff>;
254 xlnx,tri-default-2 = <0xffffffff>;
255 #gpio-cells = <2>;
256 gpio-controller;
259 gpio-leds {
260 compatible = "gpio-leds";
265 linux,default-trigger = "heartbeat";
284 gpio-restart {
285 compatible = "gpio-restart";
290 * to datasheet or trial-and-error with real hardware.
292 gpios = <&LEDs_8Bit 2 1>;
293 active-delay = <100>;
294 inactive-delay = <10>;
295 wait-delay = <100>;
299 clock-frequency = <125000000>;
300 compatible = "xlnx,xps-uartlite-1.00.a";
301 current-speed = <115200>;
303 interrupt-parent = <&xps_intc_0>;
305 port-number = <0>;
308 xlnx,data-bits = <0x8>;
310 xlnx,odd-parity = <0x0>;
311 xlnx,use-parity = <0x0>;
314 compatible = "xlnx,mdm-1.00.d";
318 xlnx,jtag-chain = <0x2>;
319 xlnx,mb-dbg-ports = <0x1>;
320 xlnx,uart-width = <0x8>;
321 xlnx,use-uart = <0x1>;
322 xlnx,write-fsl-ports = <0x0>;
325 #address-cells = <1>;
326 #size-cells = <1>;
327 compatible = "xlnx,mpmc-4.02.a";
330 compatible = "xlnx,ll-dma-1.00.a";
331 interrupt-parent = <&xps_intc_0>;
332 interrupts = < 2 2 1 2 >;
336 xps_intc_0: interrupt-controller@81800000 {
337 #interrupt-cells = <0x2>;
338 compatible = "xlnx,xps-intc-1.00.a";
339 interrupt-controller ;
341 xlnx,kind-of-intr = <0x100>;
342 xlnx,num-intr-inputs = <0x9>;
345 compatible = "xlnx,xps-timer-1.00.a";
346 interrupt-parent = <&xps_intc_0>;
347 interrupts = < 3 2 >;
349 xlnx,count-width = <0x20>;
350 xlnx,one-timer-only = <0x0>;