Lines Matching +full:dma +full:- +full:channels

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * by the VIAs (Ethernet, DSP, SCC, Sound). This includes nine DMA
7  * channels.
9  * The first seven DMA channels appear to be "one-shot" and are actually
10  * sets of two channels; one member is active while the other is being
12  * The one-shot channels are grouped together and are:
22  * The remaining two channels are handled somewhat differently. They appear
30  * machine with easy-to-find patterns and looking for them in the DMA
34  * 1999-05-25 (jmt)
52  * One-shot DMA control registers
68  * DMA channels. Add +0x10 for the second channel in the set.
70  * then flip channels and do the whole thing again.
103  * Free-running DMA registers. The only part known for sure are the bits in
107  * These registers seem to be mirrored every thirty-two bytes up until offset
112 				 * [ 16-bit ]
122 				 * bit 6  : Set to one to enable pass-thru
127 				 *          sound input DMA or zero to
130 				 *          sound output DMA or zero to
142 				 * kill all DMA at boot time so that the
148  * 0x0202 - 0x0203 is unused. Writing there
153 				 * [ 32-bit ]
156 				 * bits 12-15 : input source volume, 0 - F
157 				 * bits 16-19 : unknown, always 0x5
158 				 * bits 20-23 : input source selection:
167 				 * [ 32-bit ]
168 				 * Appears to be a read-only status register.
172 				 * [ 16-bit ]
173 				 * Unknown 16-bit value, always 0x0000.
176 				 * [ 16-bit ]
181 				 * since Apple's docs say the sound DMA
182 				 * channels are 1 bit wide.
185 				 * [ 32-bit ]
186 				 * Address of the sound input DMA buffer
189 				 * [ 32-bit ]
190 				 * Address of the sound output DMA buffer
193 				 * [ 16-bit ]
194 				 * Length of both buffers in eight-byte units.
197 				 * [ 16-bit ]
201 				 * [ 16-bit ]
202 				 * Appears to e a read-only status register.
206 				 * [ 16-bit ]