Lines Matching +full:cs +full:- +full:2
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
20 #define MCF_BUSCLK (MCF_CLK / 2)
40 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
58 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
59 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
60 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
61 #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
62 #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
63 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
64 #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
65 #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
66 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
67 #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
68 #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
69 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
70 #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
71 #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
72 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
73 #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
74 #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
75 #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
100 #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
107 #define MCFGPIO_IRQ_MAX -1
108 #define MCFGPIO_IRQ_VECBASE -1
115 #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
118 #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
121 #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */