1 // SPDX-License-Identifier: GPL-2.0
21 		if (mask & s->irr & ~s->mask) {  in pch_pic_update_irq()
22 			s->isr |= mask;  in pch_pic_update_irq()
23 			irq = s->htmsi_vector[irq];  in pch_pic_update_irq()
24 			eiointc_set_irq(s->kvm->arch.eiointc, irq, level);  in pch_pic_update_irq()
27 		if (mask & s->isr & ~s->irr) {  in pch_pic_update_irq()
28 			s->isr &= ~mask;  in pch_pic_update_irq()
29 			irq = s->htmsi_vector[irq];  in pch_pic_update_irq()
30 			eiointc_set_irq(s->kvm->arch.eiointc, irq, level);  in pch_pic_update_irq()
35 /* update batch irqs, the irq_mask is a bitmap of irqs */
40 	/* find each irq by irqs bitmap and update each irq */  in pch_pic_update_batch_irqs()
55 	spin_lock(&s->lock);  in pch_pic_set_irq()
57 		s->irr |= mask; /* set irr */  in pch_pic_set_irq()
64 		if (s->edge & mask) {  in pch_pic_set_irq()
65 			spin_unlock(&s->lock);  in pch_pic_set_irq()
68 		s->irr &= ~mask;  in pch_pic_set_irq()
71 	spin_unlock(&s->lock);  in pch_pic_set_irq()
77 	eiointc_set_irq(kvm->arch.eiointc, irq, level);  in pch_msi_set_irq()
81  * pch pic register is 64-bit, but it is accessed by 32-bit,
94  * pch pic register is 64-bit, but it is accessed by 32-bit,
125 	offset = addr - s->pch_pic_base;  in loongarch_pch_pic_read()
127 	spin_lock(&s->lock);  in loongarch_pch_pic_read()
139 		offset -= PCH_PIC_MASK_START;  in loongarch_pch_pic_read()
142 		data = pch_pic_read_reg(&s->mask, index);  in loongarch_pch_pic_read()
146 		offset -= PCH_PIC_HTMSI_EN_START;  in loongarch_pch_pic_read()
149 		data = pch_pic_read_reg(&s->htmsi_en, index);  in loongarch_pch_pic_read()
153 		offset -= PCH_PIC_EDGE_START;  in loongarch_pch_pic_read()
156 		data = pch_pic_read_reg(&s->edge, index);  in loongarch_pch_pic_read()
169 		offset -= PCH_PIC_HTMSI_VEC_START;  in loongarch_pch_pic_read()
171 		data = s->htmsi_vector[offset];  in loongarch_pch_pic_read()
179 		ret = -EINVAL;  in loongarch_pch_pic_read()
181 	spin_unlock(&s->lock);  in loongarch_pch_pic_read()
191 	struct loongarch_pch_pic *s = vcpu->kvm->arch.pch_pic;  in kvm_pch_pic_read()
195 		return -EINVAL;  in kvm_pch_pic_read()
198 	if (addr & (len - 1)) {  in kvm_pch_pic_read()
200 		return -EINVAL;  in kvm_pch_pic_read()
204 	vcpu->stat.pch_pic_read_exits++;  in kvm_pch_pic_read()
219 	offset = addr - s->pch_pic_base;  in loongarch_pch_pic_write()
221 	spin_lock(&s->lock);  in loongarch_pch_pic_write()
224 		offset -= PCH_PIC_MASK_START;  in loongarch_pch_pic_write()
227 		old = pch_pic_write_reg(&s->mask, index, data);  in loongarch_pch_pic_write()
236 		offset -= PCH_PIC_HTMSI_EN_START;  in loongarch_pch_pic_write()
238 		pch_pic_write_reg(&s->htmsi_en, index, data);  in loongarch_pch_pic_write()
241 		offset -= PCH_PIC_EDGE_START;  in loongarch_pch_pic_write()
244 		pch_pic_write_reg(&s->edge, index, data);  in loongarch_pch_pic_write()
247 		offset -= PCH_PIC_CLEAR_START;  in loongarch_pch_pic_write()
250 		old = pch_pic_read_reg(&s->irr, index);  in loongarch_pch_pic_write()
255 		irq = old & pch_pic_read_reg(&s->edge, index) & data;  in loongarch_pch_pic_write()
256 		/* write irr to the new state where irqs have been cleared */  in loongarch_pch_pic_write()
257 		pch_pic_write_reg(&s->irr, index, old & ~irq);  in loongarch_pch_pic_write()
258 		/* update cleared irqs */  in loongarch_pch_pic_write()
262 		offset -= PCH_PIC_AUTO_CTRL0_START;  in loongarch_pch_pic_write()
265 		pch_pic_write_reg(&s->auto_ctrl0, index, 0);  in loongarch_pch_pic_write()
268 		offset -= PCH_PIC_AUTO_CTRL1_START;  in loongarch_pch_pic_write()
271 		pch_pic_write_reg(&s->auto_ctrl1, index, 0);  in loongarch_pch_pic_write()
274 		offset -= PCH_PIC_ROUTE_ENTRY_START;  in loongarch_pch_pic_write()
276 		s->route_entry[offset] = 1;  in loongarch_pch_pic_write()
280 		offset -= PCH_PIC_HTMSI_VEC_START;  in loongarch_pch_pic_write()
281 		s->htmsi_vector[offset] = (u8)data;  in loongarch_pch_pic_write()
284 		offset -= PCH_PIC_POLARITY_START;  in loongarch_pch_pic_write()
287 		pch_pic_write_reg(&s->polarity, index, 0);  in loongarch_pch_pic_write()
290 		ret = -EINVAL;  in loongarch_pch_pic_write()
293 	spin_unlock(&s->lock);  in loongarch_pch_pic_write()
303 	struct loongarch_pch_pic *s = vcpu->kvm->arch.pch_pic;  in kvm_pch_pic_write()
307 		return -EINVAL;  in kvm_pch_pic_write()
310 	if (addr & (len - 1)) {  in kvm_pch_pic_write()
312 		return -EINVAL;  in kvm_pch_pic_write()
316 	vcpu->stat.pch_pic_write_exits++;  in kvm_pch_pic_write()
330 	struct kvm *kvm = dev->kvm;  in kvm_pch_pic_init()
332 	struct loongarch_pch_pic *s = dev->kvm->arch.pch_pic;  in kvm_pch_pic_init()
334 	s->pch_pic_base = addr;  in kvm_pch_pic_init()
335 	device = &s->device;  in kvm_pch_pic_init()
338 	mutex_lock(&kvm->slots_lock);  in kvm_pch_pic_init()
341 	mutex_unlock(&kvm->slots_lock);  in kvm_pch_pic_init()
343 	return (ret < 0) ? -EFAULT : 0;  in kvm_pch_pic_init()
356 	s = dev->kvm->arch.pch_pic;  in kvm_pch_pic_regs_access()
357 	addr = attr->attr;  in kvm_pch_pic_regs_access()
358 	data = (void __user *)attr->addr;  in kvm_pch_pic_regs_access()
363 		p = &s->mask;  in kvm_pch_pic_regs_access()
366 		p = &s->htmsi_en;  in kvm_pch_pic_regs_access()
369 		p = &s->edge;  in kvm_pch_pic_regs_access()
372 		p = &s->auto_ctrl0;  in kvm_pch_pic_regs_access()
375 		p = &s->auto_ctrl1;  in kvm_pch_pic_regs_access()
378 		offset = addr - PCH_PIC_ROUTE_ENTRY_START;  in kvm_pch_pic_regs_access()
379 		p = &s->route_entry[offset];  in kvm_pch_pic_regs_access()
383 		offset = addr - PCH_PIC_HTMSI_VEC_START;  in kvm_pch_pic_regs_access()
384 		p = &s->htmsi_vector[offset];  in kvm_pch_pic_regs_access()
388 		p = &s->irr;  in kvm_pch_pic_regs_access()
391 		p = &s->isr;  in kvm_pch_pic_regs_access()
394 		p = &s->polarity;  in kvm_pch_pic_regs_access()
397 		return -EINVAL;  in kvm_pch_pic_regs_access()
400 	spin_lock(&s->lock);  in kvm_pch_pic_regs_access()
404 			ret = -EFAULT;  in kvm_pch_pic_regs_access()
407 			ret = -EFAULT;  in kvm_pch_pic_regs_access()
409 	spin_unlock(&s->lock);  in kvm_pch_pic_regs_access()
417 	switch (attr->group) {  in kvm_pch_pic_get_attr()
421 		return -EINVAL;  in kvm_pch_pic_get_attr()
429 	void __user *uaddr = (void __user *)(long)attr->addr;  in kvm_pch_pic_set_attr()
431 	switch (attr->group) {  in kvm_pch_pic_set_attr()
433 		switch (attr->attr) {  in kvm_pch_pic_set_attr()
436 				return -EFAULT;  in kvm_pch_pic_set_attr()
438 			if (!dev->kvm->arch.pch_pic) {  in kvm_pch_pic_set_attr()
440 				return -ENODEV;  in kvm_pch_pic_set_attr()
445 			kvm_err("%s: unknown group (%d) attr (%lld)\n", __func__, attr->group,  in kvm_pch_pic_set_attr()
446 					attr->attr);  in kvm_pch_pic_set_attr()
447 			return -EINVAL;  in kvm_pch_pic_set_attr()
452 		return -EINVAL;  in kvm_pch_pic_set_attr()
459 	u32 nr = KVM_IRQCHIP_NUM_PINS;  in kvm_setup_default_irq_routing()  local
462 	entries = kcalloc(nr, sizeof(*entries), GFP_KERNEL);  in kvm_setup_default_irq_routing()
464 		return -ENOMEM;  in kvm_setup_default_irq_routing()
466 	for (i = 0; i < nr; i++) {  in kvm_setup_default_irq_routing()
472 	ret = kvm_set_irq_routing(kvm, entries, nr, 0);  in kvm_setup_default_irq_routing()
481 	struct kvm *kvm = dev->kvm;  in kvm_pch_pic_create()
485 	if (kvm->arch.pch_pic)  in kvm_pch_pic_create()
486 		return -EINVAL;  in kvm_pch_pic_create()
490 		return -ENOMEM;  in kvm_pch_pic_create()
494 		return -ENOMEM;  in kvm_pch_pic_create()
496 	spin_lock_init(&s->lock);  in kvm_pch_pic_create()
497 	s->kvm = kvm;  in kvm_pch_pic_create()
498 	kvm->arch.pch_pic = s;  in kvm_pch_pic_create()
508 	if (!dev || !dev->kvm || !dev->kvm->arch.pch_pic)  in kvm_pch_pic_destroy()
511 	kvm = dev->kvm;  in kvm_pch_pic_destroy()
512 	s = kvm->arch.pch_pic;  in kvm_pch_pic_destroy()
514 	kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &s->device);  in kvm_pch_pic_destroy()
519 	.name = "kvm-loongarch-pch-pic",