Lines Matching +full:ctrl +full:- +full:len
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2022-2023 Loongson Technology Corporation Limited
5 #define pr_fmt(fmt) "hw-breakpoint: " fmt
85 GEN_READ_WB_REG_CASES(CSR_CFG_CTRL, CTRL, t, val);
100 GEN_WRITE_WB_REG_CASES(CSR_CFG_CTRL, CTRL, t, val);
114 * hw_breakpoint_slot_setup - Find and setup a perf slot according to operations
123 * -ENOSPC if no slot is available/matches
124 * -EINVAL on wrong operations parameter
150 return -EINVAL;
154 return -ENOSPC;
159 memset(tsk->thread.hbp_break, 0, sizeof(tsk->thread.hbp_break));
160 memset(tsk->thread.hbp_watch, 0, sizeof(tsk->thread.hbp_watch));
169 struct thread_struct *t = &tsk->thread;
172 if (t->hbp_break[i]) {
173 unregister_hw_breakpoint(t->hbp_break[i]);
174 t->hbp_break[i] = NULL;
179 if (t->hbp_watch[i]) {
180 unregister_hw_breakpoint(t->hbp_watch[i]);
181 t->hbp_watch[i] = NULL;
189 u32 ctrl, privilege;
201 if (bp->hw.target)
202 regs = task_pt_regs(bp->hw.target);
204 if (info->ctrl.type == LOONGARCH_BREAKPOINT_EXECUTE) {
222 if (info->ctrl.type == LOONGARCH_BREAKPOINT_EXECUTE) {
223 write_wb_reg(CSR_CFG_ADDR, i, 0, info->address);
224 write_wb_reg(CSR_CFG_MASK, i, 0, info->mask);
228 write_wb_reg(CSR_CFG_ADDR, i, 1, info->address);
229 write_wb_reg(CSR_CFG_MASK, i, 1, info->mask);
231 ctrl = encode_ctrl_reg(info->ctrl);
232 write_wb_reg(CSR_CFG_CTRL, i, 1, ctrl | privilege);
236 if (bp->hw.target && test_tsk_thread_flag(bp->hw.target, TIF_LOAD_WATCH))
237 regs->csr_prmd |= CSR_PRMD_PWE;
241 if (info->ctrl.type == LOONGARCH_BREAKPOINT_EXECUTE) {
252 if (bp->hw.target)
253 regs->csr_prmd &= ~CSR_PRMD_PWE;
300 unsigned int len;
303 va = hw->address;
304 len = get_hbp_len(hw->ctrl.len);
306 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
314 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
318 switch (ctrl.type) {
332 return -EINVAL;
335 /* Len */
336 switch (ctrl.len) {
350 return -EINVAL;
364 switch (attr->bp_type) {
366 hw->ctrl.type = LOONGARCH_BREAKPOINT_EXECUTE;
369 hw->ctrl.type = LOONGARCH_BREAKPOINT_LOAD;
372 hw->ctrl.type = LOONGARCH_BREAKPOINT_STORE;
375 hw->ctrl.type = LOONGARCH_BREAKPOINT_LOAD | LOONGARCH_BREAKPOINT_STORE;
378 return -EINVAL;
381 /* Len */
382 switch (attr->bp_len) {
384 hw->ctrl.len = LOONGARCH_BREAKPOINT_LEN_1;
387 hw->ctrl.len = LOONGARCH_BREAKPOINT_LEN_2;
390 hw->ctrl.len = LOONGARCH_BREAKPOINT_LEN_4;
393 hw->ctrl.len = LOONGARCH_BREAKPOINT_LEN_8;
396 return -EINVAL;
400 hw->address = attr->bp_addr;
406 * Validate the arch-specific HW Breakpoint register settings.
420 if (hw->ctrl.type == LOONGARCH_BREAKPOINT_EXECUTE) {
422 hw->address &= ~alignment_mask;
430 u32 ctrl;
454 if ((info->ctrl.type == LOONGARCH_BREAKPOINT_EXECUTE) && (type == 0)) {
458 ctrl = read_wb_reg(CSR_CFG_CTRL, i, 1);
459 if (info->ctrl.type == LOONGARCH_BREAKPOINT_LOAD)
460 ctrl |= 0x1 << MWPnCFG3_LoadEn;
461 if (info->ctrl.type == LOONGARCH_BREAKPOINT_STORE)
462 ctrl |= 0x1 << MWPnCFG3_StoreEn;
463 write_wb_reg(CSR_CFG_CTRL, i, 1, ctrl);
465 regs->csr_prmd |= CSR_PRMD_PWE;
467 if ((info->ctrl.type == LOONGARCH_BREAKPOINT_EXECUTE) && (type == 0)) {
470 ctrl = read_wb_reg(CSR_CFG_CTRL, i, 1);
471 if (info->ctrl.type == LOONGARCH_BREAKPOINT_LOAD)
472 ctrl &= ~0x1 << MWPnCFG3_LoadEn;
473 if (info->ctrl.type == LOONGARCH_BREAKPOINT_STORE)
474 ctrl &= ~0x1 << MWPnCFG3_StoreEn;
475 write_wb_reg(CSR_CFG_CTRL, i, 1, ctrl);
477 regs->csr_prmd &= ~CSR_PRMD_PWE;
553 if (!((regs->csr_era ^ addr) & ~mask))
555 regs->csr_prmd |= CSR_PRMD_PWE;