Lines Matching +full:store +full:- +full:release

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
12 /* 5-bit Register Operand */
55 /* Load/store register (register offset) */
60 #define A64_STRB(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 8, STORE)
63 #define A64_STRH(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 16, STORE)
66 #define A64_STR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, STORE)
69 #define A64_STR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, STORE)
72 /* Load/store register (immediate offset) */
77 #define A64_STRBI(Wt, Xn, imm)  A64_LS_IMM(Wt, Xn, imm, 8, STORE)
80 #define A64_STRHI(Wt, Xn, imm)  A64_LS_IMM(Wt, Xn, imm, 16, STORE)
83 #define A64_STR32I(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 32, STORE)
86 #define A64_STR64I(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 64, STORE)
95 /* Load/store register pair */
100 /* Rn -= 16; Rn[0] = Rt; Rn[8] = Rt2; */
101 #define A64_PUSH(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, -16, STORE, PRE_INDEX)
105 /* Load/store exclusive */
117 /* [Rn] = Rt (store release); (atomic) Rs = [state] */
122 /* Load-acquire & store-release */
136 /* [Rn] = Rt (store release) */
162 /* Rt = [Rn] (load acquire); [Rn] <op>= Rs (store release) */
167 /* Rt = [Rn] (load acquire); [Rn] = Rs (store release) */
169 /* Rs = CAS(Rn, Rs, Rt) (load acquire & store release) */
187 /* Rn - imm12; set condition flags */
204 	A64_UBFM(sf, Rd, Rn, (unsigned)-(shift) % sz, sz - 1 - (shift)); \
239 /* Rd = -Rm */
241 /* Rn - Rm; set condition flags */
244 /* Data-processing (1 source) */
252 /* Data-processing (2 source) */
262 /* Data-processing (3 source) */
266 /* Rd = Ra - Rn * Rm */