108 #define A64_LSX(sf, Rt, Rn, Rs, type) \  argument
109 	aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \
114 /* [Rn] = Rt; (atomic) Rs = [state] */
115 #define A64_STXR(sf, Rt, Rn, Rs) \  argument
116 	A64_LSX(sf, Rt, Rn, Rs, STORE_EX)
117 /* [Rn] = Rt (store release); (atomic) Rs = [state] */
118 #define A64_STLXR(sf, Rt, Rn, Rs) \  argument
119 	aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \
128 #define A64_ST_OP(sf, Rn, Rs, op) \  argument
129 	aarch64_insn_gen_atomic_ld_op(A64_ZR, Rn, Rs, \
132 /* [Rn] <op>= Rs */
133 #define A64_STADD(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, ADD)  argument
134 #define A64_STCLR(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, CLR)  argument
135 #define A64_STEOR(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, EOR)  argument
136 #define A64_STSET(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, SET)  argument
138 #define A64_LD_OP_AL(sf, Rt, Rn, Rs, op) \  argument
139 	aarch64_insn_gen_atomic_ld_op(Rt, Rn, Rs, \
142 /* Rt = [Rn] (load acquire); [Rn] <op>= Rs (store release) */
143 #define A64_LDADDAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, ADD)  argument
144 #define A64_LDCLRAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, CLR)  argument
145 #define A64_LDEORAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, EOR)  argument
146 #define A64_LDSETAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, SET)  argument
147 /* Rt = [Rn] (load acquire); [Rn] = Rs (store release) */
148 #define A64_SWPAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, SWP)  argument
149 /* Rs = CAS(Rn, Rs, Rt) (load acquire & store release) */
150 #define A64_CASAL(sf, Rt, Rn, Rs) \  argument
151 	aarch64_insn_gen_cas(Rt, Rn, Rs, A64_SIZE(sf), \