Lines Matching refs:reset_val
2296 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
2297 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
2315 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
2328 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 },
2478 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
2480 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
2485 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
2491 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
2492 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 },
2558 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },
2559 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
2587 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
2594 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
2606 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility },
2607 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility },
2645 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
2806 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
2810 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),
2811 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),
2813 EL2_REG(MDCR_EL2, access_rw, reset_val, 0),
2814 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
2815 EL2_REG_VNCR(HSTR_EL2, reset_val, 0),
2816 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0),
2817 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0),
2818 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0),
2819 EL2_REG_VNCR(HACR_EL2, reset_val, 0),
2821 { SYS_DESC(SYS_ZCR_EL2), .access = access_zcr_el2, .reset = reset_val,
2824 EL2_REG_VNCR(HCRX_EL2, reset_val, 0),
2826 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
2827 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
2828 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
2829 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0),
2830 EL2_REG_VNCR(VTCR_EL2, reset_val, 0),
2833 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0),
2834 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0),
2835 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0),
2836 EL2_REG_REDIR(SPSR_EL2, reset_val, 0),
2837 EL2_REG_REDIR(ELR_EL2, reset_val, 0),
2847 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
2848 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
2849 EL2_REG_REDIR(ESR_EL2, reset_val, 0),
2850 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 },
2852 EL2_REG_REDIR(FAR_EL2, reset_val, 0),
2853 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
2855 EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
2856 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
2858 EL2_REG(VBAR_EL2, access_rw, reset_val, 0),
2859 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0),
2862 EL2_REG_VNCR(ICH_HCR_EL2, reset_val, 0),
2864 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0),
2865 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0),
2867 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0),
2868 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0),