950 		v &= ~masks->mask[sr].res0;  in kvm_vcpu_apply_reg_masks()
957 static __always_inline void set_sysreg_masks(struct kvm *kvm, int sr, u64 res0, u64 res1)  in set_sysreg_masks()  argument
965 	kvm->arch.sysreg_masks->mask[i].res0 = res0;  in set_sysreg_masks()
972 	u64 res0, res1;  in kvm_init_nv_sysregs()  local
987 	res0 = res1 = 0;  in kvm_init_nv_sysregs()
989 		res0 |= GENMASK(63, 56);  in kvm_init_nv_sysregs()
991 		res0 |= VTTBR_CNP_BIT;  in kvm_init_nv_sysregs()
992 	set_sysreg_masks(kvm, VTTBR_EL2, res0, res1);  in kvm_init_nv_sysregs()
995 	res0 = GENMASK(63, 32) | GENMASK(30, 20);  in kvm_init_nv_sysregs()
997 	set_sysreg_masks(kvm, VTCR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1000 	res0 = GENMASK(63, 40) | GENMASK(30, 24);  in kvm_init_nv_sysregs()
1002 	set_sysreg_masks(kvm, VMPIDR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1005 	res0 = BIT(48);  in kvm_init_nv_sysregs()
1008 		res0 |= GENMASK(63, 59);  in kvm_init_nv_sysregs()
1010 		res0 |= (HCR_TID5 | HCR_DCT | HCR_ATA);  in kvm_init_nv_sysregs()
1012 		res0 |= (HCR_TTLBIS | HCR_TTLBOS);  in kvm_init_nv_sysregs()
1015 		res0 |= HCR_ENSCXT;  in kvm_init_nv_sysregs()
1017 		res0 |= (HCR_TOCU | HCR_TICAB | HCR_TID4);  in kvm_init_nv_sysregs()
1019 		res0 |= HCR_AMVOFFEN;  in kvm_init_nv_sysregs()
1021 		res0 |= HCR_FIEN;  in kvm_init_nv_sysregs()
1023 		res0 |= HCR_FWB;  in kvm_init_nv_sysregs()
1025 		res0 |= HCR_NV2;  in kvm_init_nv_sysregs()
1027 		res0 |= (HCR_AT | HCR_NV1 | HCR_NV);  in kvm_init_nv_sysregs()
1030 		res0 |= (HCR_API | HCR_APK);  in kvm_init_nv_sysregs()
1032 		res0 |= BIT(39);  in kvm_init_nv_sysregs()
1034 		res0 |= (HCR_TEA | HCR_TERR);  in kvm_init_nv_sysregs()
1036 		res0 |= HCR_TLOR;  in kvm_init_nv_sysregs()
1039 	set_sysreg_masks(kvm, HCR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1042 	res0 = HCRX_EL2_RES0;  in kvm_init_nv_sysregs()
1045 		res0 |= HCRX_EL2_PACMEn;  in kvm_init_nv_sysregs()
1047 		res0 |= HCRX_EL2_EnFPM;  in kvm_init_nv_sysregs()
1049 		res0 |= HCRX_EL2_GCSEn;  in kvm_init_nv_sysregs()
1051 		res0 |= HCRX_EL2_EnIDCP128;  in kvm_init_nv_sysregs()
1053 		res0 |= (HCRX_EL2_EnSDERR | HCRX_EL2_EnSNERR);  in kvm_init_nv_sysregs()
1055 		res0 |= HCRX_EL2_TMEA;  in kvm_init_nv_sysregs()
1057 		res0 |= HCRX_EL2_D128En;  in kvm_init_nv_sysregs()
1059 		res0 |= HCRX_EL2_PTTWI;  in kvm_init_nv_sysregs()
1061 		res0 |= HCRX_EL2_SCTLR2En;  in kvm_init_nv_sysregs()
1063 		res0 |= HCRX_EL2_TCR2En;  in kvm_init_nv_sysregs()
1065 		res0 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2);  in kvm_init_nv_sysregs()
1067 		res0 |= HCRX_EL2_CMOW;  in kvm_init_nv_sysregs()
1069 		res0 |= (HCRX_EL2_VFNMI | HCRX_EL2_VINMI | HCRX_EL2_TALLINT);  in kvm_init_nv_sysregs()
1072 		res0 |= HCRX_EL2_SMPME;  in kvm_init_nv_sysregs()
1074 		res0 |= (HCRX_EL2_FGTnXS | HCRX_EL2_FnXS);  in kvm_init_nv_sysregs()
1076 		res0 |= HCRX_EL2_EnASR;  in kvm_init_nv_sysregs()
1078 		res0 |= HCRX_EL2_EnALS;  in kvm_init_nv_sysregs()
1080 		res0 |= HCRX_EL2_EnAS0;  in kvm_init_nv_sysregs()
1081 	set_sysreg_masks(kvm, HCRX_EL2, res0, res1);  in kvm_init_nv_sysregs()
1084 	res0 = res1 = 0;  in kvm_init_nv_sysregs()
1087 		res0 |= (HFGxTR_EL2_APDAKey | HFGxTR_EL2_APDBKey |  in kvm_init_nv_sysregs()
1091 		res0 |= (HFGxTR_EL2_LORC_EL1 | HFGxTR_EL2_LOREA_EL1 |  in kvm_init_nv_sysregs()
1096 		res0 |= (HFGxTR_EL2_SCXTNUM_EL1 | HFGxTR_EL2_SCXTNUM_EL0);  in kvm_init_nv_sysregs()
1098 		res0 |= HFGxTR_EL2_ICC_IGRPENn_EL1;  in kvm_init_nv_sysregs()
1100 		res0 |= (HFGxTR_EL2_ERRIDR_EL1 | HFGxTR_EL2_ERRSELR_EL1 |  in kvm_init_nv_sysregs()
1106 		res0 |= HFGxTR_EL2_nACCDATA_EL1;  in kvm_init_nv_sysregs()
1108 		res0 |= (HFGxTR_EL2_nGCS_EL0 | HFGxTR_EL2_nGCS_EL1);  in kvm_init_nv_sysregs()
1110 		res0 |= (HFGxTR_EL2_nSMPRI_EL1 | HFGxTR_EL2_nTPIDR2_EL0);  in kvm_init_nv_sysregs()
1112 		res0 |= HFGxTR_EL2_nRCWMASK_EL1;  in kvm_init_nv_sysregs()
1114 		res0 |= (HFGxTR_EL2_nPIRE0_EL1 | HFGxTR_EL2_nPIR_EL1);  in kvm_init_nv_sysregs()
1116 		res0 |= (HFGxTR_EL2_nPOR_EL0 | HFGxTR_EL2_nPOR_EL1);  in kvm_init_nv_sysregs()
1118 		res0 |= HFGxTR_EL2_nS2POR_EL1;  in kvm_init_nv_sysregs()
1120 		res0 |= (HFGxTR_EL2_nMAIR2_EL1 | HFGxTR_EL2_nAMAIR2_EL1);  in kvm_init_nv_sysregs()
1121 	set_sysreg_masks(kvm, HFGRTR_EL2, res0 | __HFGRTR_EL2_RES0, res1);  in kvm_init_nv_sysregs()
1122 	set_sysreg_masks(kvm, HFGWTR_EL2, res0 | __HFGWTR_EL2_RES0, res1);  in kvm_init_nv_sysregs()
1125 	res0 = res1 = 0;  in kvm_init_nv_sysregs()
1127 		res0 |= HDFGRTR_EL2_OSDLR_EL1;  in kvm_init_nv_sysregs()
1129 		res0 |= (HDFGRTR_EL2_PMEVCNTRn_EL0 | HDFGRTR_EL2_PMEVTYPERn_EL0 |  in kvm_init_nv_sysregs()
1136 		res0 |= (HDFGRTR_EL2_PMBLIMITR_EL1 | HDFGRTR_EL2_PMBPTR_EL1 |  in kvm_init_nv_sysregs()
1143 		res0 |= (HDFGRTR_EL2_TRC | HDFGRTR_EL2_TRCAUTHSTATUS |  in kvm_init_nv_sysregs()
1151 		res0 |= (HDFGRTR_EL2_TRBBASER_EL1 | HDFGRTR_EL2_TRBIDR_EL1 |  in kvm_init_nv_sysregs()
1156 		res0 |= (HDFGRTR_EL2_nBRBIDR | HDFGRTR_EL2_nBRBCTL |  in kvm_init_nv_sysregs()
1159 		res0 |= HDFGRTR_EL2_nPMSNEVFR_EL1;  in kvm_init_nv_sysregs()
1160 	set_sysreg_masks(kvm, HDFGRTR_EL2, res0 | HDFGRTR_EL2_RES0, res1);  in kvm_init_nv_sysregs()
1164 		res0 |= (HDFGWTR_EL2_PMCR_EL0 | HDFGWTR_EL2_PMSWINC_EL0);  in kvm_init_nv_sysregs()
1166 		res0 |= HDFGWTR_EL2_TRCOSLAR;  in kvm_init_nv_sysregs()
1168 		res0 |= HDFGWTR_EL2_TRFCR_EL1;  in kvm_init_nv_sysregs()
1169 	set_sysreg_masks(kvm, HFGWTR_EL2, res0 | HDFGWTR_EL2_RES0, res1);  in kvm_init_nv_sysregs()
1172 	res0 = HFGITR_EL2_RES0;  in kvm_init_nv_sysregs()
1175 		res0 |= HFGITR_EL2_DCCVADP;  in kvm_init_nv_sysregs()
1177 		res0 |= (HFGITR_EL2_ATS1E1RP | HFGITR_EL2_ATS1E1WP);  in kvm_init_nv_sysregs()
1179 		res0 |= (HFGITR_EL2_TLBIRVAALE1OS | HFGITR_EL2_TLBIRVALE1OS |  in kvm_init_nv_sysregs()
1185 		res0 |= (HFGITR_EL2_TLBIRVAALE1 | HFGITR_EL2_TLBIRVALE1 |  in kvm_init_nv_sysregs()
1192 		res0 |= (HFGITR_EL2_CFPRCTX | HFGITR_EL2_DVPRCTX |  in kvm_init_nv_sysregs()
1195 		res0 |= (HFGITR_EL2_nBRBINJ | HFGITR_EL2_nBRBIALL);  in kvm_init_nv_sysregs()
1197 		res0 |= (HFGITR_EL2_nGCSPUSHM_EL1 | HFGITR_EL2_nGCSSTR_EL1 |  in kvm_init_nv_sysregs()
1200 		res0 |= HFGITR_EL2_COSPRCTX;  in kvm_init_nv_sysregs()
1202 		res0 |= HFGITR_EL2_ATS1E1A;  in kvm_init_nv_sysregs()
1203 	set_sysreg_masks(kvm, HFGITR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1206 	res0 = HAFGRTR_EL2_RES0;  in kvm_init_nv_sysregs()
1209 		res0 |= ~(res0 | res1);  in kvm_init_nv_sysregs()
1210 	set_sysreg_masks(kvm, HAFGRTR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1213 	res0 = TCR2_EL2_RES0;  in kvm_init_nv_sysregs()
1216 		res0 |= (TCR2_EL2_DisCH0 | TCR2_EL2_DisCH1 | TCR2_EL2_D128);  in kvm_init_nv_sysregs()
1218 		res0 |= TCR2_EL2_AMEC1 | TCR2_EL2_AMEC0;  in kvm_init_nv_sysregs()
1220 		res0 |= TCR2_EL2_HAFT;  in kvm_init_nv_sysregs()
1222 		res0 |= TCR2_EL2_PTTWI | TCR2_EL2_PnCH;  in kvm_init_nv_sysregs()
1224 		res0 |= TCR2_EL2_AIE;  in kvm_init_nv_sysregs()
1226 		res0 |= TCR2_EL2_POE | TCR2_EL2_E0POE;  in kvm_init_nv_sysregs()
1228 		res0 |= TCR2_EL2_PIE;  in kvm_init_nv_sysregs()
1230 		res0 |= (TCR2_EL2_E0POE | TCR2_EL2_D128 |  in kvm_init_nv_sysregs()
1232 	set_sysreg_masks(kvm, TCR2_EL2, res0, res1);  in kvm_init_nv_sysregs()
1235 	res0 = SCTLR_EL1_RES0;  in kvm_init_nv_sysregs()
1238 		res0 |= SCTLR_EL1_EPAN;  in kvm_init_nv_sysregs()
1239 	set_sysreg_masks(kvm, SCTLR_EL1, res0, res1);  in kvm_init_nv_sysregs()
1242 	res0 = MDCR_EL2_RES0;  in kvm_init_nv_sysregs()
1245 		res0 |= (MDCR_EL2_HPMN | MDCR_EL2_TPMCR |  in kvm_init_nv_sysregs()
1248 		res0 |= MDCR_EL2_E2PB | MDCR_EL2_TPMS;  in kvm_init_nv_sysregs()
1250 		res0 |= MDCR_EL2_EnSPM;  in kvm_init_nv_sysregs()
1252 		res0 |= MDCR_EL2_HPMD;  in kvm_init_nv_sysregs()
1254 		res0 |= MDCR_EL2_TTRF;  in kvm_init_nv_sysregs()
1256 		res0 |= MDCR_EL2_HCCD | MDCR_EL2_HLP;  in kvm_init_nv_sysregs()
1258 		res0 |= MDCR_EL2_E2TB;  in kvm_init_nv_sysregs()
1260 		res0 |= MDCR_EL2_TDCC;  in kvm_init_nv_sysregs()
1263 		res0 |= MDCR_EL2_MTPME;  in kvm_init_nv_sysregs()
1265 		res0 |= MDCR_EL2_HPMFZO;  in kvm_init_nv_sysregs()
1267 		res0 |= MDCR_EL2_PMSSE;  in kvm_init_nv_sysregs()
1269 		res0 |= MDCR_EL2_HPMFZS;  in kvm_init_nv_sysregs()
1271 		res0 |= MDCR_EL2_PMEE;  in kvm_init_nv_sysregs()
1273 		res0 |= MDCR_EL2_EBWE;  in kvm_init_nv_sysregs()
1275 		res0 |= MDCR_EL2_EnSTEPOP;  in kvm_init_nv_sysregs()
1276 	set_sysreg_masks(kvm, MDCR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1279 	res0 = GENMASK(63, 20);  in kvm_init_nv_sysregs()
1282 		res0 |= CNTHCTL_CNTPMASK | CNTHCTL_CNTVMASK;  in kvm_init_nv_sysregs()
1284 		res0 |= CNTHCTL_ECV;  in kvm_init_nv_sysregs()
1286 			res0 |= (CNTHCTL_EL1TVT | CNTHCTL_EL1TVCT |  in kvm_init_nv_sysregs()
1290 		res0 |= GENMASK(11, 8);  in kvm_init_nv_sysregs()
1291 	set_sysreg_masks(kvm, CNTHCTL_EL2, res0, res1);  in kvm_init_nv_sysregs()