Lines Matching full:res1
1635 v |= masks->mask[sr].res1; in kvm_vcpu_apply_reg_masks()
1641 static __always_inline void set_sysreg_masks(struct kvm *kvm, int sr, u64 res0, u64 res1) in set_sysreg_masks() argument
1650 kvm->arch.sysreg_masks->mask[i].res1 = res1; in set_sysreg_masks()
1656 u64 res0, res1; in kvm_init_nv_sysregs() local
1669 res0 = res1 = 0; in kvm_init_nv_sysregs()
1674 set_sysreg_masks(kvm, VTTBR_EL2, res0, res1); in kvm_init_nv_sysregs()
1678 res1 = BIT(31); in kvm_init_nv_sysregs()
1679 set_sysreg_masks(kvm, VTCR_EL2, res0, res1); in kvm_init_nv_sysregs()
1683 res1 = BIT(31); in kvm_init_nv_sysregs()
1684 set_sysreg_masks(kvm, VMPIDR_EL2, res0, res1); in kvm_init_nv_sysregs()
1687 get_reg_fixed_bits(kvm, HCR_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1688 set_sysreg_masks(kvm, HCR_EL2, res0, res1); in kvm_init_nv_sysregs()
1691 get_reg_fixed_bits(kvm, HCRX_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1692 set_sysreg_masks(kvm, HCRX_EL2, res0, res1); in kvm_init_nv_sysregs()
1695 get_reg_fixed_bits(kvm, HFGRTR_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1696 set_sysreg_masks(kvm, HFGRTR_EL2, res0, res1); in kvm_init_nv_sysregs()
1697 get_reg_fixed_bits(kvm, HFGWTR_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1698 set_sysreg_masks(kvm, HFGWTR_EL2, res0, res1); in kvm_init_nv_sysregs()
1701 get_reg_fixed_bits(kvm, HDFGRTR_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1702 set_sysreg_masks(kvm, HDFGRTR_EL2, res0, res1); in kvm_init_nv_sysregs()
1703 get_reg_fixed_bits(kvm, HDFGWTR_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1704 set_sysreg_masks(kvm, HDFGWTR_EL2, res0, res1); in kvm_init_nv_sysregs()
1707 get_reg_fixed_bits(kvm, HFGITR_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1708 set_sysreg_masks(kvm, HFGITR_EL2, res0, res1); in kvm_init_nv_sysregs()
1711 get_reg_fixed_bits(kvm, HAFGRTR_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1712 set_sysreg_masks(kvm, HAFGRTR_EL2, res0, res1); in kvm_init_nv_sysregs()
1715 get_reg_fixed_bits(kvm, HFGRTR2_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1716 set_sysreg_masks(kvm, HFGRTR2_EL2, res0, res1); in kvm_init_nv_sysregs()
1717 get_reg_fixed_bits(kvm, HFGWTR2_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1718 set_sysreg_masks(kvm, HFGWTR2_EL2, res0, res1); in kvm_init_nv_sysregs()
1721 get_reg_fixed_bits(kvm, HDFGRTR2_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1722 set_sysreg_masks(kvm, HDFGRTR2_EL2, res0, res1); in kvm_init_nv_sysregs()
1723 get_reg_fixed_bits(kvm, HDFGWTR2_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1724 set_sysreg_masks(kvm, HDFGWTR2_EL2, res0, res1); in kvm_init_nv_sysregs()
1727 get_reg_fixed_bits(kvm, HFGITR2_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1728 set_sysreg_masks(kvm, HFGITR2_EL2, res0, res1); in kvm_init_nv_sysregs()
1731 get_reg_fixed_bits(kvm, TCR2_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1732 set_sysreg_masks(kvm, TCR2_EL2, res0, res1); in kvm_init_nv_sysregs()
1735 get_reg_fixed_bits(kvm, SCTLR_EL1, &res0, &res1); in kvm_init_nv_sysregs()
1736 set_sysreg_masks(kvm, SCTLR_EL1, res0, res1); in kvm_init_nv_sysregs()
1739 get_reg_fixed_bits(kvm, SCTLR2_EL1, &res0, &res1); in kvm_init_nv_sysregs()
1740 set_sysreg_masks(kvm, SCTLR2_EL1, res0, res1); in kvm_init_nv_sysregs()
1741 get_reg_fixed_bits(kvm, SCTLR2_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1742 set_sysreg_masks(kvm, SCTLR2_EL2, res0, res1); in kvm_init_nv_sysregs()
1745 get_reg_fixed_bits(kvm, MDCR_EL2, &res0, &res1); in kvm_init_nv_sysregs()
1746 set_sysreg_masks(kvm, MDCR_EL2, res0, res1); in kvm_init_nv_sysregs()
1750 res1 = 0; in kvm_init_nv_sysregs()
1761 set_sysreg_masks(kvm, CNTHCTL_EL2, res0, res1); in kvm_init_nv_sysregs()
1765 res1 = ICH_HCR_EL2_RES1; in kvm_init_nv_sysregs()
1770 set_sysreg_masks(kvm, ICH_HCR_EL2, res0, res1); in kvm_init_nv_sysregs()