69  * This performs the exception entry at a given EL (@target_mode), stashing PC
74  * When an exception is taken, most PSTATE fields are left unchanged in the
133 	// PSTATE.UAO is set to zero upon any exception to AArch64  in enter_exception64()
143 	// PSTATE.SS is set to zero upon any exception to AArch64  in enter_exception64()
146 	// PSTATE.IL is set to zero upon any exception to AArch64  in enter_exception64()
149 	// PSTATE.SSBS is set to SCTLR_ELx.DSSBS upon any exception to AArch64  in enter_exception64()
154 	// PSTATE.BTYPE is set to zero upon any exception to AArch64  in enter_exception64()
169  * When an exception is taken, most CPSR fields are left unchanged in the
200 	// CPSR.IT[7:0] are set to zero upon any exception  in get_except32_cpsr()
206 	// CPSR.SSBS is set to SCTLR.DSSBS upon any exception  in get_except32_cpsr()
220 	// CPSR.IL is set to zero upon any exception  in get_except32_cpsr()
225 	// CPSR.IT[7:0] are set to zero upon any exception  in get_except32_cpsr()
228 	// CPSR.E is set to SCTLR.EE upon any exception  in get_except32_cpsr()
234 	// CPSR.A is unchanged upon an exception to Undefined, Supervisor  in get_except32_cpsr()
235 	// CPSR.A is set upon an exception to other modes  in get_except32_cpsr()
242 	// CPSR.I is set upon any exception  in get_except32_cpsr()
247 	// CPSR.F is set upon an exception to FIQ  in get_except32_cpsr()
248 	// CPSR.F is unchanged upon an exception to other modes  in get_except32_cpsr()
255 	// CPSR.T is set to SCTLR.TE upon any exception  in get_except32_cpsr()
304 	/* Branch to exception vector */  in enter_exception32()
364  * Adjust the guest PC (and potentially exception state) depending on