19 	sign_extend32(((insn) & 0x3ffffff) << 2, 27)
22 	sign_extend32(((insn >> 5) & 0x7ffff) << 2, 20)
25 	sign_extend32(((insn >> 5) & 0x7ffff) << 2, 20)
28 	sign_extend32(((insn >> 5) & 0x3fff) << 2, 15)
31 	sign_extend32(((insn >> 5) & 0x7ffff) << 2, 20)
55 	int err = 0;  in update_lr()
70 	int xn = opcode & 0x1f;  in check_cbz()
73 	    (get_x_reg(regs, xn) == 0) : (get_w_reg(regs, xn) == 0);  in check_cbz()
78 	int xn = opcode & 0x1f;  in check_cbnz()
81 	    (get_x_reg(regs, xn) != 0) : (get_w_reg(regs, xn) != 0);  in check_cbnz()
86 	int xn = opcode & 0x1f;  in check_tbz()
87 	int bit_pos = ((opcode & (1 << 31)) >> 26) | ((opcode >> 19) & 0x1f);  in check_tbz()
89 	return ((get_x_reg(regs, xn) >> bit_pos) & 0x1) == 0;  in check_tbz()
94 	int xn = opcode & 0x1f;  in check_tbnz()
95 	int bit_pos = ((opcode & (1 << 31)) >> 26) | ((opcode >> 19) & 0x1f);  in check_tbnz()
97 	return ((get_x_reg(regs, xn) >> bit_pos) & 0x1) != 0;  in check_tbnz()
108 	xn = opcode & 0x1f;  in simulate_adr_adrp()
109 	imm = ((opcode >> 3) & 0x1ffffc) | ((opcode >> 29) & 0x3);  in simulate_adr_adrp()
111 	if (opcode & 0x80000000)  in simulate_adr_adrp()
112 		val = (imm<<12) + (addr & 0xfffffffffffff000);  in simulate_adr_adrp()
138 	if (aarch32_opcode_cond_checks[opcode & 0xf](regs->pstate & 0xffffffff))  in simulate_b_cond()
147 	int xn = (opcode >> 5) & 0x1f;  in simulate_br_blr()
150 	if (((opcode >> 21) & 0x3) == 1)  in simulate_br_blr()
161 	int err = 0;  in simulate_ret()
162 	int xn = (opcode >> 5) & 0x1f;  in simulate_ret()
209 	int xn = opcode & 0x1f;  in simulate_ldr_literal()
225 	int xn = opcode & 0x1f;  in simulate_ldrsw_literal()