Lines Matching +full:0 +full:x29
34 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
42 .if \el == 0
65 tbnz x0, #THREAD_SHIFT, 0f
70 0:
125 nop // Patched to SMC/HVC #0
198 .if \el == 0
204 stp x0, x1, [sp, #16 * 0]
218 stp x28, x29, [sp, #16 * 14]
220 .if \el == 0
280 .endif /* \el == 0 */
290 .if \el == 0
296 add x29, sp, #S_STACKFRAME
307 .if \el == 0
336 .if \el != 0
364 .if \el == 0
373 mrs x29, contextidr_el1
374 msr contextidr_el1, x29
409 apply_ssbd 0, x0, x1
414 ldp x0, x1, [sp, #16 * 0]
428 ldp x28, x29, [sp, #16 * 14]
430 .if \el == 0
434 msr far_el1, x29
436 ldr_this_cpu x30, this_cpu_vector, x29
437 tramp_alias x29, tramp_exit
441 br x29
450 .if \el == 0
492 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
530 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0
531 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0
532 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
533 kernel_ventry 0, t, 64, error // Error 64-bit EL0
535 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0
536 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0
537 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
538 kernel_ventry 0, t, 32, error // Error 32-bit EL0
575 .if \el == 0
596 entry_handler 0, t, 64, sync
597 entry_handler 0, t, 64, irq
598 entry_handler 0, t, 64, fiq
599 entry_handler 0, t, 64, error
601 entry_handler 0, t, 32, sync
602 entry_handler 0, t, 32, irq
603 entry_handler 0, t, 32, fiq
604 entry_handler 0, t, 32, error
616 kernel_exit 0
671 * instruction to load the upper 16 bits (which must be 0xFFFF).
679 #define BHB_MITIGATION_NONE 0
742 .space 0x400
770 tramp_unmap_kernel x29
771 mrs x29, far_el1 // restore x29
795 tramp_ventry .Lvector_start\@, 64, 0, \bhb
798 tramp_ventry .Lvector_start\@, 32, 0, \bhb
833 stp x29, x9, [x8], #16
841 ldp x29, x9, [x8], #16
883 stp x29, x30, [sp, #-16]!
884 mov x29, sp
898 mov sp, x29
899 ldp x29, x30, [sp], #16
915 smc #0
917 99: hvc #0
994 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1039 and x0, x3, #0xc
1042 csel x29, x29, xzr, eq // fp, or zero
1045 stp x29, x4, [sp, #-16]!
1046 mov x29, sp
1055 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]