Lines Matching +full:0 +full:x22
34 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
42 .if \el == 0
65 tbnz x0, #THREAD_SHIFT, 0f
70 0:
125 nop // Patched to SMC/HVC #0
198 .if \el == 0
204 stp x0, x1, [sp, #16 * 0]
215 stp x22, x23, [sp, #16 * 11]
220 .if \el == 0
235 check_mte_async_tcf x22, x23, x0
249 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23
259 apply_ssbd 1, x22, x23
261 mte_set_kernel_gcr x22, x23
280 .endif /* \el == 0 */
281 mrs x22, elr_el1
290 .if \el == 0
304 stp x22, x23, [sp, #S_PC]
307 .if \el == 0
330 * x22 - aborted PC
336 .if \el != 0
356 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
364 .if \el == 0
367 tst x22, #PSR_MODE32_BIT // native task?
409 apply_ssbd 0, x0, x1
413 msr spsr_el1, x22
414 ldp x0, x1, [sp, #16 * 0]
425 ldp x22, x23, [sp, #16 * 11]
430 .if \el == 0
450 .if \el == 0
490 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
492 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
530 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0
531 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0
532 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
533 kernel_ventry 0, t, 64, error // Error 64-bit EL0
535 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0
536 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0
537 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
538 kernel_ventry 0, t, 32, error // Error 32-bit EL0
575 .if \el == 0
596 entry_handler 0, t, 64, sync
597 entry_handler 0, t, 64, irq
598 entry_handler 0, t, 64, fiq
599 entry_handler 0, t, 64, error
601 entry_handler 0, t, 32, sync
602 entry_handler 0, t, 32, irq
603 entry_handler 0, t, 32, fiq
604 entry_handler 0, t, 32, error
616 kernel_exit 0
671 * instruction to load the upper 16 bits (which must be 0xFFFF).
679 #define BHB_MITIGATION_NONE 0
742 .space 0x400
795 tramp_ventry .Lvector_start\@, 64, 0, \bhb
798 tramp_ventry .Lvector_start\@, 32, 0, \bhb
829 stp x21, x22, [x8], #16
837 ldp x21, x22, [x8], #16
915 smc #0
917 99: hvc #0
991 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
1039 and x0, x3, #0xc