Lines Matching +full:half +full:- +full:dbm
1 // SPDX-License-Identifier: GPL-2.0-only
9 * there's a little bit of over-abstraction that tends to obscure what's going
14 * user-visible instructions are available only on a subset of the available
18 * snapshot state to indicate the lowest-common denominator of the feature,
31 * - Mismatched features are *always* sanitised to a "safe" value, which
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
50 * - KVM exposes its own view of the feature registers to guest operating
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
120 * after the MMU (with the idmap) was enabled. create_init_idmap() - which
121 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG -
130 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
137 * seen at least one CPU capable of 32-bit EL0.
142 * Mask of CPUs supporting 32-bit EL0.
149 /* file-wide pr_fmt adds "CPU features: " prefix */ in dump_cpu_features()
155 BIT(reg##_##field##_WIDTH - 1) : \
156 BIT(reg##_##field##_WIDTH)) - 1)
158 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1)
170 * an implicit maximum that depends on the sign-ess of the field.
173 * will be limited to the positive half only.
183 * matching a non-implemented property.
424 * Page size not being supported at Stage-2 is not fatal. You
429 * advertises a given granule size at Stage-2 (value 2) on some
430 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
446 * along with it and treat them as non-strict.
525 * Linux can handle differing I-cache policies. Userspace JITs will
527 * If we have differing I-cache policies, report it as the weakest - VIPT.
735 * id_isar[1-3], id_mmfr[1-3]
867 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; in search_cmp_ftr_reg()
871 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
876 * returns - Upon success, matching ftr_reg entry for id.
877 * - NULL on failure. It is upto the caller to decide
890 return ret->reg; in get_arm64_ftr_reg_nowarn()
895 * get_arm64_ftr_reg - Looks up a feature register entry using
898 * returns - Upon success, matching ftr_reg entry for id.
899 * - NULL on failure but with an WARN_ON().
908 * Requesting a non-existent register search is an error. Warn in get_arm64_ftr_reg()
921 reg |= (ftr_val << ftrp->shift) & mask; in arm64_ftr_set_value()
930 switch (ftrp->type) { in arm64_ftr_safe_value()
932 ret = ftrp->safe_val; in arm64_ftr_safe_value()
957 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; in sort_ftr_regs()
964 for (; ftr_bits->width != 0; ftr_bits++, j++) { in sort_ftr_regs()
965 unsigned int width = ftr_reg->ftr_bits[j].width; in sort_ftr_regs()
966 unsigned int shift = ftr_reg->ftr_bits[j].shift; in sort_ftr_regs()
971 ftr_reg->name, shift); in sort_ftr_regs()
980 prev_shift = ftr_reg->ftr_bits[j - 1].shift; in sort_ftr_regs()
983 ftr_reg->name, shift); in sort_ftr_regs()
997 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); in sort_ftr_regs()
1005 * RES0 for the system-wide value, and must strictly match.
1020 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { in init_cpu_ftr_reg()
1023 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); in init_cpu_ftr_reg()
1025 if ((ftr_mask & reg->override->mask) == ftr_mask) { in init_cpu_ftr_reg()
1031 reg->override->mask &= ~ftr_mask; in init_cpu_ftr_reg()
1032 reg->override->val &= ~ftr_mask; in init_cpu_ftr_reg()
1045 reg->name, in init_cpu_ftr_reg()
1046 ftrp->shift + ftrp->width - 1, in init_cpu_ftr_reg()
1047 ftrp->shift, str, in init_cpu_ftr_reg()
1048 tmp & (BIT(ftrp->width) - 1)); in init_cpu_ftr_reg()
1049 } else if ((ftr_mask & reg->override->val) == ftr_mask) { in init_cpu_ftr_reg()
1050 reg->override->val &= ~ftr_mask; in init_cpu_ftr_reg()
1052 reg->name, in init_cpu_ftr_reg()
1053 ftrp->shift + ftrp->width - 1, in init_cpu_ftr_reg()
1054 ftrp->shift); in init_cpu_ftr_reg()
1060 if (!ftrp->strict) in init_cpu_ftr_reg()
1062 if (ftrp->visible) in init_cpu_ftr_reg()
1065 reg->user_val = arm64_ftr_set_value(ftrp, in init_cpu_ftr_reg()
1066 reg->user_val, in init_cpu_ftr_reg()
1067 ftrp->safe_val); in init_cpu_ftr_reg()
1072 reg->sys_val = val; in init_cpu_ftr_reg()
1073 reg->strict_mask = strict_mask; in init_cpu_ftr_reg()
1074 reg->user_mask = user_mask; in init_cpu_ftr_reg()
1083 for (; caps->matches; caps++) { in init_cpucap_indirect_list_from_array()
1084 if (WARN(caps->capability >= ARM64_NCAPS, in init_cpucap_indirect_list_from_array()
1085 "Invalid capability %d\n", caps->capability)) in init_cpucap_indirect_list_from_array()
1087 if (WARN(cpucap_ptrs[caps->capability], in init_cpucap_indirect_list_from_array()
1089 caps->capability)) in init_cpucap_indirect_list_from_array()
1091 cpucap_ptrs[caps->capability] = caps; in init_cpucap_indirect_list_from_array()
1105 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); in init_32bit_cpu_features()
1106 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); in init_32bit_cpu_features()
1107 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); in init_32bit_cpu_features()
1108 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); in init_32bit_cpu_features()
1109 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); in init_32bit_cpu_features()
1110 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); in init_32bit_cpu_features()
1111 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); in init_32bit_cpu_features()
1112 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); in init_32bit_cpu_features()
1113 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); in init_32bit_cpu_features()
1114 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); in init_32bit_cpu_features()
1115 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); in init_32bit_cpu_features()
1116 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); in init_32bit_cpu_features()
1117 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); in init_32bit_cpu_features()
1118 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); in init_32bit_cpu_features()
1119 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); in init_32bit_cpu_features()
1120 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); in init_32bit_cpu_features()
1121 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); in init_32bit_cpu_features()
1122 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); in init_32bit_cpu_features()
1123 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); in init_32bit_cpu_features()
1124 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); in init_32bit_cpu_features()
1125 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); in init_32bit_cpu_features()
1148 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); in detect_system_supports_pseudo_nmi()
1149 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { in detect_system_supports_pseudo_nmi()
1150 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); in detect_system_supports_pseudo_nmi()
1164 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); in init_cpu_features()
1165 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); in init_cpu_features()
1166 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); in init_cpu_features()
1167 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); in init_cpu_features()
1168 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); in init_cpu_features()
1169 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); in init_cpu_features()
1170 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); in init_cpu_features()
1171 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); in init_cpu_features()
1172 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); in init_cpu_features()
1173 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); in init_cpu_features()
1174 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); in init_cpu_features()
1175 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); in init_cpu_features()
1176 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); in init_cpu_features()
1177 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); in init_cpu_features()
1178 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); in init_cpu_features()
1179 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); in init_cpu_features()
1180 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); in init_cpu_features()
1181 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); in init_cpu_features()
1182 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); in init_cpu_features()
1183 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); in init_cpu_features()
1185 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) in init_cpu_features()
1186 init_32bit_cpu_features(&info->aarch32); in init_cpu_features()
1207 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); in init_cpu_features()
1208 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); in init_cpu_features()
1211 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) in init_cpu_features()
1212 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); in init_cpu_features()
1219 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { in update_cpu_ftr_reg()
1220 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); in update_cpu_ftr_reg()
1227 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); in update_cpu_ftr_reg()
1240 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) in check_update_ftr_reg()
1243 regp->name, boot, cpu, val); in check_update_ftr_reg()
1255 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { in relax_cpu_ftr_reg()
1256 if (ftrp->shift == field) { in relax_cpu_ftr_reg()
1257 regp->strict_mask &= ~arm64_ftr_mask(ftrp); in relax_cpu_ftr_reg()
1263 WARN_ON(!ftrp->width); in relax_cpu_ftr_reg()
1274 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) in lazy_init_32bit_cpu_features()
1277 boot->aarch32 = info->aarch32; in lazy_init_32bit_cpu_features()
1278 init_32bit_cpu_features(&boot->aarch32); in lazy_init_32bit_cpu_features()
1290 * EL1-dependent register fields to avoid spurious sanity check fails. in update_32bit_cpu_features()
1302 info->reg_id_dfr0, boot->reg_id_dfr0); in update_32bit_cpu_features()
1304 info->reg_id_dfr1, boot->reg_id_dfr1); in update_32bit_cpu_features()
1306 info->reg_id_isar0, boot->reg_id_isar0); in update_32bit_cpu_features()
1308 info->reg_id_isar1, boot->reg_id_isar1); in update_32bit_cpu_features()
1310 info->reg_id_isar2, boot->reg_id_isar2); in update_32bit_cpu_features()
1312 info->reg_id_isar3, boot->reg_id_isar3); in update_32bit_cpu_features()
1314 info->reg_id_isar4, boot->reg_id_isar4); in update_32bit_cpu_features()
1316 info->reg_id_isar5, boot->reg_id_isar5); in update_32bit_cpu_features()
1318 info->reg_id_isar6, boot->reg_id_isar6); in update_32bit_cpu_features()
1326 info->reg_id_mmfr0, boot->reg_id_mmfr0); in update_32bit_cpu_features()
1328 info->reg_id_mmfr1, boot->reg_id_mmfr1); in update_32bit_cpu_features()
1330 info->reg_id_mmfr2, boot->reg_id_mmfr2); in update_32bit_cpu_features()
1332 info->reg_id_mmfr3, boot->reg_id_mmfr3); in update_32bit_cpu_features()
1334 info->reg_id_mmfr4, boot->reg_id_mmfr4); in update_32bit_cpu_features()
1336 info->reg_id_mmfr5, boot->reg_id_mmfr5); in update_32bit_cpu_features()
1338 info->reg_id_pfr0, boot->reg_id_pfr0); in update_32bit_cpu_features()
1340 info->reg_id_pfr1, boot->reg_id_pfr1); in update_32bit_cpu_features()
1342 info->reg_id_pfr2, boot->reg_id_pfr2); in update_32bit_cpu_features()
1344 info->reg_mvfr0, boot->reg_mvfr0); in update_32bit_cpu_features()
1346 info->reg_mvfr1, boot->reg_mvfr1); in update_32bit_cpu_features()
1348 info->reg_mvfr2, boot->reg_mvfr2); in update_32bit_cpu_features()
1355 * non-boot CPU. Also performs SANITY checks to make sure that there
1365 * The kernel can handle differing I-cache policies, but otherwise in update_cpu_features()
1370 info->reg_ctr, boot->reg_ctr); in update_cpu_features()
1378 info->reg_dczid, boot->reg_dczid); in update_cpu_features()
1382 info->reg_cntfrq, boot->reg_cntfrq); in update_cpu_features()
1385 * The kernel uses self-hosted debug features and expects CPUs to in update_cpu_features()
1391 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); in update_cpu_features()
1393 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); in update_cpu_features()
1395 * Even in big.LITTLE, processors should be identical instruction-set in update_cpu_features()
1399 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); in update_cpu_features()
1401 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); in update_cpu_features()
1403 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); in update_cpu_features()
1405 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); in update_cpu_features()
1413 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); in update_cpu_features()
1415 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); in update_cpu_features()
1417 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); in update_cpu_features()
1419 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); in update_cpu_features()
1421 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); in update_cpu_features()
1424 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); in update_cpu_features()
1426 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); in update_cpu_features()
1428 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); in update_cpu_features()
1431 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); in update_cpu_features()
1434 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); in update_cpu_features()
1437 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); in update_cpu_features()
1463 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); in update_cpu_features()
1465 info->reg_mpamidr, boot->reg_mpamidr); in update_cpu_features()
1474 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { in update_cpu_features()
1476 info->reg_gmid, boot->reg_gmid); in update_cpu_features()
1487 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { in update_cpu_features()
1489 taint |= update_32bit_cpu_features(cpu, &info->aarch32, in update_cpu_features()
1490 &boot->aarch32); in update_cpu_features()
1509 return regp->sys_val; in read_sanitised_ftr_reg()
1517 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1577 val &= ~regp->override->mask; in __read_sysreg_by_encoding()
1578 val |= (regp->override->val & regp->override->mask); in __read_sysreg_by_encoding()
1584 #include <linux/irqchip/arm-gic-v3.h>
1598 val = cpuid_feature_extract_field_width(reg, entry->field_pos, in feature_matches()
1599 entry->field_width, in feature_matches()
1600 entry->sign); in feature_matches()
1602 tmp = entry->min_field_value; in feature_matches()
1603 tmp <<= entry->field_pos; in feature_matches()
1605 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, in feature_matches()
1606 entry->field_width, in feature_matches()
1607 entry->sign); in feature_matches()
1609 tmp = entry->max_field_value; in feature_matches()
1610 tmp <<= entry->field_pos; in feature_matches()
1612 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, in feature_matches()
1613 entry->field_width, in feature_matches()
1614 entry->sign); in feature_matches()
1624 return read_sanitised_ftr_reg(entry->sys_reg); in read_scoped_sysreg()
1626 return __read_sysreg_by_encoding(entry->sys_reg); in read_scoped_sysreg()
1636 regp = get_arm64_ftr_reg(entry->sys_reg); in has_user_cpuid_feature()
1640 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, in has_user_cpuid_feature()
1641 entry->field_pos, in has_user_cpuid_feature()
1642 entry->field_width); in has_user_cpuid_feature()
1711 pr_info("detected: 32-bit EL0 Support\n"); in has_32bit_el0()
1726 entry->desc); in has_useable_gicv3_cpuif()
1773 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP in has_useable_cnp()
1825 * ThunderX leads to apparent I-cache corruption of kernel text, which in unmap_kernel_at_el0()
1834 __kpti_forced = -1; in unmap_kernel_at_el0()
1847 __kpti_forced = -1; in unmap_kernel_at_el0()
1943 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT))
1954 kpti_ng_temp_alloc -= PAGE_SIZE; in kpti_ng_pgd_alloc()
1980 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); in __kpti_install_ng_mappings()
1989 // +--------+-/-------+-/------ +-/------ +-\\\--------+ in __kpti_install_ng_mappings()
1991 // +--------+-\-------+-\------ +-\------ +-///--------+ in __kpti_install_ng_mappings()
1997 // to be used as a ad-hoc fixmap. in __kpti_install_ng_mappings()
2023 * We don't need to rewrite the page-tables if either we've done in kpti_install_ng_mappings()
2057 __kpti_forced = enabled ? 1 : -1; in parse_kpti()
2076 /* List of CPUs which have broken DBM support. */ in cpu_has_broken_dbm()
2110 * DBM is a non-conflicting feature. i.e, the kernel can safely in has_hw_dbm()
2160 * The AMU extension is a non-conflicting feature: the kernel can in has_amu()
2193 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to in cpu_copy_el2regs()
2207 pr_warn("unavailable: %s\n", cap->desc); in has_nested_virt_support()
2224 * as possible. This list is therefore an allow-list of known-good in has_bbml2_noabort()
2230 * Note that implementations can only be considered "known-good" if their in has_bbml2_noabort()
2282 * The ptr-auth feature levels are not intercompatible with lower in has_address_auth_cpucap()
2283 * levels. Hence we must match ptr-auth feature level of the secondary in has_address_auth_cpucap()
2291 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), in has_address_auth_cpucap()
2292 entry->field_pos, entry->sign); in has_address_auth_cpucap()
2294 return boot_val >= entry->min_field_value; in has_address_auth_cpucap()
2296 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), in has_address_auth_cpucap()
2297 entry->field_pos, entry->sign); in has_address_auth_cpucap()
2298 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); in has_address_auth_cpucap()
2378 * Use of X16/X17 for tail-calls and trampolines that jump to in bti_enable()
2416 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; in user_feature_fixup()
2424 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; in user_feature_fixup()
2478 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); in cpucap_late_cpu_optional()
2484 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); in cpucap_late_cpu_permitted()
2490 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); in cpucap_panic_on_conflict()
2508 * which is configured unrestricted. This avoids priority-inversion in cpu_enable_mpam()
2615 .desc = "32-bit EL1 Support",
2716 .desc = "Stage-2 Force Write-Back",
2744 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM)
2929 .desc = "RCpc load-acquire (LDAPR)",
3014 .desc = "Stage-1 Permission Indirection Extension (S1PIE)",
3040 .desc = "52-bit Virtual Addressing for KVM (LPA2)",
3059 .desc = "52-bit Virtual Addressing (LVA)",
3062 .desc = "52-bit Virtual Addressing (LPA2)",
3094 .desc = "Stage-1 Permission Overlay Extension (S1POE)",
3351 * check is future proof, by making sure value is non-zero. in compat_has_neon()
3393 switch (cap->hwcap_type) { in cap_set_elf_hwcap()
3395 cpu_set_feature(cap->hwcap); in cap_set_elf_hwcap()
3399 compat_elf_hwcap |= (u32)cap->hwcap; in cap_set_elf_hwcap()
3402 compat_elf_hwcap2 |= (u32)cap->hwcap; in cap_set_elf_hwcap()
3416 switch (cap->hwcap_type) { in cpus_have_elf_hwcap()
3418 rc = cpu_have_feature(cap->hwcap); in cpus_have_elf_hwcap()
3422 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; in cpus_have_elf_hwcap()
3425 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; in cpus_have_elf_hwcap()
3440 for (; hwcaps->matches; hwcaps++) in setup_elf_hwcaps()
3441 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) in setup_elf_hwcaps()
3457 if (!caps || !(caps->type & scope_mask)) in update_cpu_capabilities()
3461 caps_set = cpus_have_cap(caps->capability); in update_cpu_capabilities()
3465 * Unless it's a match-all CPUs feature, avoid probing if in update_cpu_capabilities()
3472 * A match-all CPUs capability is only set when probing the in update_cpu_capabilities()
3479 if (!caps->matches(caps, cpucap_default_scope(caps))) { in update_cpu_capabilities()
3481 __clear_bit(caps->capability, system_cpucaps); in update_cpu_capabilities()
3486 * Match-all CPUs capabilities are logged later when the in update_cpu_capabilities()
3489 if (!match_all && caps->desc && !caps->cpus) in update_cpu_capabilities()
3490 pr_info("detected: %s\n", caps->desc); in update_cpu_capabilities()
3492 __set_bit(caps->capability, system_cpucaps); in update_cpu_capabilities()
3494 if (boot_cpu && (caps->type & SCOPE_BOOT_CPU)) in update_cpu_capabilities()
3495 set_bit(caps->capability, boot_cpucaps); in update_cpu_capabilities()
3514 if (!(cap->type & non_boot_scope)) in cpu_enable_non_boot_scope_capabilities()
3517 if (cap->cpu_enable) in cpu_enable_non_boot_scope_capabilities()
3518 cap->cpu_enable(cap); in cpu_enable_non_boot_scope_capabilities()
3538 if (!caps || !(caps->type & scope_mask) || in enable_cpu_capabilities()
3539 !cpus_have_cap(caps->capability)) in enable_cpu_capabilities()
3542 if (boot_scope && caps->cpu_enable) in enable_cpu_capabilities()
3552 caps->cpu_enable(caps); in enable_cpu_capabilities()
3556 * For all non-boot scope capabilities, use stop_machine() in enable_cpu_capabilities()
3581 if (!caps || !(caps->type & scope_mask)) in verify_local_cpu_caps()
3584 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); in verify_local_cpu_caps()
3585 system_has_cap = cpus_have_cap(caps->capability); in verify_local_cpu_caps()
3600 if (caps->cpu_enable) in verify_local_cpu_caps()
3601 caps->cpu_enable(caps); in verify_local_cpu_caps()
3614 smp_processor_id(), caps->capability, in verify_local_cpu_caps()
3615 caps->desc, system_has_cap, cpu_has_cap); in verify_local_cpu_caps()
3639 for (; caps->matches; caps++) in __verify_local_elf_hwcaps()
3640 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { in __verify_local_elf_hwcaps()
3642 smp_processor_id(), caps->desc); in __verify_local_elf_hwcaps()
3799 return cap->matches(cap, SCOPE_LOCAL_CPU); in this_cpu_has_cap()
3808 * - The system wide safe registers are set with all the SMP CPUs and,
3809 * - The SYSTEM_FEATURE system_cpucaps may not have been set.
3817 return cap->matches(cap, SCOPE_SYSTEM); in __system_matches_cap()
3875 * Detect broken pseudo-NMI. Must be called _before_ the call to in setup_boot_cpu_features()
3887 * The system-wide safe feature register values have been finalized. in setup_system_capabilities()
3898 if (!caps || !caps->desc) in setup_system_capabilities()
3905 if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids) in setup_system_capabilities()
3907 caps->desc, cpumask_pr_args(caps->cpus)); in setup_system_capabilities()
3909 /* Log match-all CPUs capabilities */ in setup_system_capabilities()
3911 cpus_have_cap(caps->capability)) in setup_system_capabilities()
3912 pr_info("detected: %s\n", caps->desc); in setup_system_capabilities()
3956 * The first 32-bit-capable CPU we detected and so can no longer in enable_mismatched_32bit_el0()
3957 * be offlined by userspace. -1 indicates we haven't yet onlined in enable_mismatched_32bit_el0()
3958 * a 32-bit-capable CPU. in enable_mismatched_32bit_el0()
3960 static int lucky_winner = -1; in enable_mismatched_32bit_el0()
3965 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { in enable_mismatched_32bit_el0()
3967 pr_info("Treating adaptive-ticks CPU %u as 64-bit only\n", cpu); in enable_mismatched_32bit_el0()
3985 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting in enable_mismatched_32bit_el0()
3986 * every CPU in the system for a 32-bit task. in enable_mismatched_32bit_el0()
3990 get_cpu_device(lucky_winner)->offline_disabled = true; in enable_mismatched_32bit_el0()
3993 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", in enable_mismatched_32bit_el0()
4004 return -ENOMEM; in init_32bit_el0_mask()
4019 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7]
4020 * See Table C5-6 System instruction encodings for System register accesses,
4050 return -EINVAL; in emulate_id_reg()
4061 return -EINVAL; in emulate_sys_reg()