1 // SPDX-License-Identifier: GPL-2.0-only
16  * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
29 #define LDSTHD_I_BIT(i)	(i & (1 << 22))		/* double/half-word immed */
39 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
58 		offset.un = -offset.un;  in do_alignment_finish_ldst()
64 		regs->regs[RN_BITS(instr)] = addr;  in do_alignment_finish_ldst()
75 		/* ARMv7 Thumb-2 32-bit LDRD/STRD */  in do_alignment_ldrdstrd()
91 		regs->regs[rd] = val;  in do_alignment_ldrdstrd()
92 		regs->regs[rd2] = val2;  in do_alignment_ldrdstrd()
94 		if (put_user(regs->regs[rd], (u32 __user *)addr) ||  in do_alignment_ldrdstrd()
95 		    put_user(regs->regs[rd2], (u32 __user *)(addr + 4)))  in do_alignment_ldrdstrd()
104  * There are 4 variants of this instruction:
107  *              ------ increasing address ----->
121 	/* count the number of registers in the mask to be transferred */  in do_alignment_ldmstm()
125 	newaddr = eaddr = regs->regs[rn];  in do_alignment_ldmstm()
128 		nr_regs = -nr_regs;  in do_alignment_ldmstm()
143 					regs->regs[rd] = val;  in do_alignment_ldmstm()
145 					regs->pc = val;  in do_alignment_ldmstm()
148 				 * The PC register has a bias of +8 in ARM mode  in do_alignment_ldmstm()
150 				 * of the value of PC should account for this.  in do_alignment_ldmstm()
154 				val = (rd < 15) ? regs->regs[rd] : regs->pc + 8;  in do_alignment_ldmstm()
162 		regs->regs[rn] = newaddr;  in do_alignment_ldmstm()
168  * Convert Thumb multi-word load/store instruction forms to equivalent ARM
172  * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
177  * 2. If for some reason we're passed an non-ld/st Thumb instruction to
203 			static const u32 subset[4] = {  in thumb2arm()  local
209 			return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |  in thumb2arm()
220  * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
224  * @pinstr: original Thumb-2 instruction; returns new handlable instruction
252 			const u32 subset[2] = {  in do_alignment_t32_to_handler()  local
256 			*pinstr = subset[L] | (1<<RD_BITS(instr));  in do_alignment_t32_to_handler()
267 		poffset->un = (tinst2 & 0xff) << 2;  in do_alignment_t32_to_handler()
329 		if (IS_T32(tinstr)) { /* Thumb-2 32-bit */  in do_compat_alignment_fixup()
348 			offset.un = regs->regs[RM_BITS(instr)];  in do_compat_alignment_fixup()
357 	case 0x08000000:	/* ldm or stm, or thumb-2 32bit instruction */  in do_compat_alignment_fixup()
379 	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->pc);  in do_compat_alignment_fixup()