20 #define CODING_BITS(i)	(i & 0x0e000000)
27 #define LDST_P_EQ_U(i)	((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
35 #define REGMASK_BITS(i)	(i & 0xffff)
37 #define BAD_INSTR 	0xdeadc0de
41 	(((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
48 #define TYPE_ERROR	0
74 	if ((instr & 0xfe000000) == 0xe8000000) {  in do_alignment_ldrdstrd()
76 		rd2 = (instr >> 8) & 0xf;  in do_alignment_ldrdstrd()
81 		load = ((instr & 0xf0) == 0xd0);  in do_alignment_ldrdstrd()
136 	for (regbits = REGMASK_BITS(instr), rd = 0; regbits;  in do_alignment_ldmstm()
178  *    decode, we return 0xdeadc0de. This should never happen under normal
187 	switch ((tinstr & 0xf800) >> 11) {  in thumb2arm()
189 	case 0xc000 >> 11:				/* 7.1.51 STMIA */  in thumb2arm()
190 	case 0xc800 >> 11:				/* 7.1.25 LDMIA */  in thumb2arm()
193 			u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;  in thumb2arm()
195 			return 0xe8800000 | W | (L<<20) | (Rn<<16) |  in thumb2arm()
200 	case 0xb000 >> 11:				/* 7.1.48 PUSH */  in thumb2arm()
201 	case 0xb800 >> 11:				/* 7.1.47 POP */  in thumb2arm()
202 		if ((tinstr & (3 << 9)) == 0x0400) {  in thumb2arm()
204 				0xe92d0000,	/* STMDB sp!,{registers} */  in thumb2arm()
205 				0xe92d4000,	/* STMDB sp!,{registers,lr} */  in thumb2arm()
206 				0xe8bd0000,	/* LDMIA sp!,{registers} */  in thumb2arm()
207 				0xe8bd8000	/* LDMIA sp!,{registers,pc} */  in thumb2arm()
237 	u16 tinst1 = (instr >> 16) & 0xffff;  in do_alignment_t32_to_handler()
238 	u16 tinst2 = instr & 0xffff;  in do_alignment_t32_to_handler()
240 	switch (tinst1 & 0xffe0) {  in do_alignment_t32_to_handler()
242 	case 0xe880:		/* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */  in do_alignment_t32_to_handler()
243 	case 0xe8a0:		/* ...above writeback version */  in do_alignment_t32_to_handler()
244 	case 0xe900:		/* STMDB/STMFD, LDMDB/LDMEA */  in do_alignment_t32_to_handler()
245 	case 0xe920:		/* ...above writeback version */  in do_alignment_t32_to_handler()
249 	case 0xf840:		/* POP/PUSH T3 (single register) */  in do_alignment_t32_to_handler()
250 		if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {  in do_alignment_t32_to_handler()
253 				0xe92d0000,	/* STMDB sp!,{registers} */  in do_alignment_t32_to_handler()
254 				0xe8bd0000,	/* LDMIA sp!,{registers} */  in do_alignment_t32_to_handler()
263 	case 0xe860:  in do_alignment_t32_to_handler()
264 	case 0xe960:  in do_alignment_t32_to_handler()
265 	case 0xe8e0:  in do_alignment_t32_to_handler()
266 	case 0xe9e0:  in do_alignment_t32_to_handler()
267 		poffset->un = (tinst2 & 0xff) << 2;  in do_alignment_t32_to_handler()
270 	case 0xe940:  in do_alignment_t32_to_handler()
271 	case 0xe9c0:  in do_alignment_t32_to_handler()
286 	__le32 instr = 0;  in alignment_get_arm()
294 	return 0;  in alignment_get_arm()
299 	__le16 instr = 0;  in alignment_get_thumb()
307 	return 0;  in alignment_get_thumb()
316 	u32 instr = 0;  in do_compat_alignment_fixup()
318 	int thumb2_32b = 0;  in do_compat_alignment_fixup()
344 	case 0x00000000:	/* 3.13.4 load/store instruction extensions */  in do_compat_alignment_fixup()
346 			offset.un = (instr & 0xf00) >> 4 | (instr & 15);  in do_compat_alignment_fixup()
350 		if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */  in do_compat_alignment_fixup()
351 		    (instr & 0x001000f0) == 0x000000f0)   /* STRD */  in do_compat_alignment_fixup()
357 	case 0x08000000:	/* ldm or stm, or thumb-2 32bit instruction */  in do_compat_alignment_fixup()
359 			offset.un = 0;  in do_compat_alignment_fixup()
362 			offset.un = 0;  in do_compat_alignment_fixup()
384 	return 0;  in do_compat_alignment_fixup()