Lines Matching refs:x0
20 mov_q x0, \val
39 orr x0, x0, #HCR_E2H
41 msr_hcr_el2 x0
46 mov_q x0, INIT_SCTLR_EL2_MMU_OFF
47 msr sctlr_el2, x0
52 mrs x0, id_aa64mmfr1_el1
53 ubfx x0, x0, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4
54 cbz x0, .Lskip_hcrx_\@
55 mov_q x0, (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM)
61 orr x0, x0, #HCRX_EL2_GCSEn
64 msr_s SYS_HCRX_EL2, x0
86 mov x0, #3 // Enable EL1 physical timers
88 lsl x0, x0, #10
90 msr cnthctl_el2, x0
96 ubfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
97 cmp x0, #ID_AA64DFR0_EL1_PMUVer_NI
98 ccmp x0, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne
100 mrs x0, pmcr_el0 // Disable debug access traps
101 ubfx x0, x0, #11, #5 // to EL2 and allow access to
103 csel x2, xzr, x0, eq // all PMU counters from EL1
106 ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
107 cbz x0, .Lskip_spe_\@ // Skip if SPE not present
109 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2,
110 and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT)
111 cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical
112 mov x0, #(1 << PMSCR_EL2_PCT_SHIFT | \
114 msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter
116 mov x0, #MDCR_EL2_E2PB_MASK
117 orr x2, x2, x0 // If we don't have VHE, then
122 ubfx x0, x1, #ID_AA64DFR0_EL1_TraceBuffer_SHIFT, #4
123 cbz x0, .Lskip_trace_\@ // Skip if TraceBuffer is not present
125 mrs_s x0, SYS_TRBIDR_EL1
126 and x0, x0, TRBIDR_EL1_P
127 cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2
129 mov x0, #MDCR_EL2_E2TB_MASK
130 orr x2, x2, x0 // allow the EL1&0 translation
140 ubfx x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4
141 cbz x0, .Lskip_lor_\@
153 mrs x0, id_aa64pfr0_el1
154 ubfx x0, x0, #ID_AA64PFR0_EL1_GIC_SHIFT, #4
155 cbz x0, .Lskip_gicv3_\@
157 mrs_s x0, SYS_ICC_SRE_EL2
158 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
159 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
160 msr_s SYS_ICC_SRE_EL2, x0
162 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back,
163 tbz x0, #0, .Lskip_gicv3_\@ // and check that it sticks
170 mrs_s x0, SYS_ID_AA64PFR2_EL1
171 ubfx x0, x0, #ID_AA64PFR2_EL1_GCIE_SHIFT, #4
172 cbz x0, .Lskip_gicv5_\@
174 mov x0, #(ICH_HFGITR_EL2_GICRCDNMIA | \
185 msr_s SYS_ICH_HFGITR_EL2, x0 // Disable instruction traps
186 mov_q x0, (ICH_HFGRTR_EL2_ICC_PPI_ACTIVERn_EL1 | \
199 msr_s SYS_ICH_HFGRTR_EL2, x0 // Disable reg read traps
200 mov_q x0, (ICH_HFGWTR_EL2_ICC_PPI_ACTIVERn_EL1 | \
208 msr_s SYS_ICH_HFGWTR_EL2, x0 // Disable reg write traps
218 mrs x0, midr_el1
220 msr vpidr_el2, x0
227 mov x0, #CPACR_EL1_FPEN
228 msr cpacr_el1, x0
231 mov x0, #0x33ff
232 msr cptr_el2, x0 // Disable copro. traps to EL2
253 mov_q x0, BRBCR_ELx_CC | BRBCR_ELx_MPRED
254 msr_s SYS_BRBCR_EL2, x0
264 mov x0, xzr
271 orr x0, x0, #HDFGRTR_EL2_nPMSNEVFR_EL1_MASK
285 orr x0, x0, #HDFGRTR_EL2_nBRBDATA_MASK
295 orr x0, x0, #HDFGRTR_EL2_nBRBCTL_MASK
299 orr x0, x0, #HDFGRTR_EL2_nBRBIDR_MASK
304 msr_s SYS_HDFGRTR_EL2, x0
307 mov x0, xzr
326 orr x0, x0, #HFGRTR_EL2_nSMPRI_EL1_MASK
327 orr x0, x0, #HFGRTR_EL2_nTPIDR2_EL0_MASK
335 orr x0, x0, #HFGRTR_EL2_nPIR_EL1
336 orr x0, x0, #HFGRTR_EL2_nPIRE0_EL1
344 orr x0, x0, #HFGRTR_EL2_nPOR_EL0
353 orr x0, x0, #HFGRTR_EL2_nGCS_EL1_MASK
354 orr x0, x0, #HFGRTR_EL2_nGCS_EL0_MASK
359 msr_s SYS_HFGRTR_EL2, x0
360 msr_s SYS_HFGWTR_EL2, x0
380 mov x0, xzr
386 orr x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0
387 orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0
388 orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1
390 msr_s SYS_HDFGRTR2_EL2, x0
391 msr_s SYS_HDFGWTR2_EL2, x0
467 mrs_s x0, SYS_MPAMIDR_EL1
468 tbz x0, #MPAMIDR_EL1_HAS_HCR_SHIFT, .Lskip_mpam_\@ // skip if no MPAMHCR reg
485 mrs x0, cpacr_el1 // Disable SVE traps
486 orr x0, x0, #CPACR_EL1_ZEN
487 msr cpacr_el1, x0
491 mrs x0, cptr_el2 // Disable SVE traps
492 bic x0, x0, #CPTR_EL2_TZ
493 msr cptr_el2, x0
506 mrs x0, cpacr_el1 // Disable SME traps
507 orr x0, x0, #CPACR_EL1_SMEN
508 msr cpacr_el1, x0
512 mrs x0, cptr_el2 // Disable SME traps
513 bic x0, x0, #CPTR_EL2_TSM
514 msr cptr_el2, x0
523 mov x0, #0 // SMCR controls
530 orr x0, x0, SMCR_ELx_FA64_MASK
537 orr x0, x0, SMCR_ELx_EZT0_MASK
540 orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector
541 msr_s SYS_SMCR_EL2, x0 // length for EL1.