Lines Matching refs:orr
64 orr x0, x0, #HCR_E2H
85 orr x0, x0, #HCRX_EL2_GCSEn
92 orr x0, x0, #HCRX_EL2_EnALS
95 orr x0, x0, #HCRX_EL2_EnASR
158 orr x2, x2, x0 // If we don't have VHE, then
171 orr x2, x2, x0 // allow the EL1&0 translation
199 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
200 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
311 orr x0, x0, #HDFGRTR_EL2_nPMSNEVFR_EL1_MASK
312 orr x2, x2, #HDFGWTR_EL2_nPMSNEVFR_EL1_MASK
325 orr x0, x0, #HDFGRTR_EL2_nBRBDATA_MASK
332 orr x2, x2, #HDFGWTR_EL2_nBRBDATA_MASK
335 orr x0, x0, #HDFGRTR_EL2_nBRBCTL_MASK
336 orr x2, x2, #HDFGWTR_EL2_nBRBCTL_MASK
339 orr x0, x0, #HDFGRTR_EL2_nBRBIDR_MASK
355 orr x2, x2, #HFGITR_EL2_nBRBIALL_MASK
358 orr x2, x2, #HFGITR_EL2_nBRBINJ_MASK
366 orr x0, x0, #HFGRTR_EL2_nSMPRI_EL1_MASK
367 orr x0, x0, #HFGRTR_EL2_nTPIDR2_EL0_MASK
375 orr x0, x0, #HFGRTR_EL2_nPIR_EL1
376 orr x0, x0, #HFGRTR_EL2_nPIRE0_EL1
384 orr x0, x0, #HFGRTR_EL2_nPOR_EL0
393 orr x0, x0, #HFGRTR_EL2_nGCS_EL1_MASK
394 orr x0, x0, #HFGRTR_EL2_nGCS_EL0_MASK
428 orr x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0
429 orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0
430 orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1
431 orr x2, x2, #HDFGWTR2_EL2_nPMICNTR_EL0
432 orr x2, x2, #HDFGWTR2_EL2_nPMICFILTR_EL0
433 orr x2, x2, #HDFGWTR2_EL2_nPMUACR_EL1
435 orr x2, x2, #HDFGWTR2_EL2_nPMZR_EL0
445 orr x0, x0, #HDFGRTR2_EL2_nPMSDSFR_EL1
446 orr x2, x2, #HDFGWTR2_EL2_nPMSDSFR_EL1
548 orr x0, x0, #CPACR_EL1_ZEN
569 orr x0, x0, #CPACR_EL1_SMEN
581 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
592 orr x0, x0, SMCR_ELx_FA64_MASK
599 orr x0, x0, SMCR_ELx_EZT0_MASK
602 orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector